On Monday, November 02, 2015 at 01:26:09 PM, Stefan Roese wrote:
> The SR1500 board is a CycloneV based board, similar to the EBV
> SoCrates, equipped with the following devices:
>
> - SPI NOR
> - eMMC
> - Ethernet
>
> Signed-off-by: Stefan Roese <s...@denx.de>
> Cc: Marek Vasut <ma...@denx.de>
> Cc: Pavel Machek <pa...@denx.de>
> Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> ---
> v3:
> - Removed README.socfpga changes
> - Removed board specific commands
Really ? ;-)
> - Change CONFIG_LOADADDR to 0x01000000 as suggested by Dinh
>
> v2:
> - Addressed various review comments from Marek:
> - Added chapter about SPL integration for SoC FPGA in doc/README.socfpga
> - Delay after PHY reset deassertion added
> - Reshuffle of the code for the PHY test code (fixes and cleanup)
> - Cleanup of the board config header
>
> arch/arm/dts/Makefile | 4 +-
> arch/arm/dts/socfpga_cyclone5_sr1500.dts | 101 +++++
> arch/arm/mach-socfpga/Kconfig | 6 +
> board/sr1500/MAINTAINERS | 6 +
> board/sr1500/Makefile | 7 +
> board/sr1500/qts/iocsr_config.h | 660
> +++++++++++++++++++++++++++++++ board/sr1500/qts/pinmux_config.h |
> 219 ++++++++++
> board/sr1500/qts/pll_config.h | 85 ++++
> board/sr1500/qts/sdram_config.h | 341 ++++++++++++++++
> board/sr1500/socfpga.c | 151 +++++++
> configs/socfpga_sr1500_defconfig | 17 +
> include/configs/socfpga_sr1500.h | 113 ++++++
> 12 files changed, 1709 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/socfpga_cyclone5_sr1500.dts
> create mode 100644 board/sr1500/MAINTAINERS
> create mode 100644 board/sr1500/Makefile
> create mode 100644 board/sr1500/qts/iocsr_config.h
> create mode 100644 board/sr1500/qts/pinmux_config.h
> create mode 100644 board/sr1500/qts/pll_config.h
> create mode 100644 board/sr1500/qts/sdram_config.h
> create mode 100644 board/sr1500/socfpga.c
> create mode 100644 configs/socfpga_sr1500_defconfig
> create mode 100644 include/configs/socfpga_sr1500.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ddc6a05..b77aab48 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -74,7 +74,9 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
> \
> socfpga_cyclone5_socdk.dtb \
> socfpga_cyclone5_de0_nano_soc.dtb \
> socfpga_cyclone5_sockit.dtb \
> - socfpga_cyclone5_socrates.dtb
> + socfpga_cyclone5_socrates.dtb \
> + socfpga_cyclone5_sr1500.dtb
> +
> dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
> dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
> dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
> diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts
> b/arch/arm/dts/socfpga_cyclone5_sr1500.dts new file mode 100644
> index 0000000..3729ca0
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
> @@ -0,0 +1,101 @@
> +/*
> + * Copyright (C) 2015 Stefan Roese <s...@denx.de>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include "socfpga_cyclone5.dtsi"
> +
> +/ {
> + model = "SoCFPGA Cyclone V SR1500";
> + compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5",
> "altr,socfpga"; +
> + chosen {
> + bootargs = "console=ttyS0,115200";
> + };
> +
> + aliases {
> + /*
> + * This allows the ethaddr uboot environmnet variable
> + * contents to be added to the gmac1 device tree blob.
> + */
> + ethernet0 = &gmac1;
> + };
> +
> + memory@0 {
> + name = "memory";
> + device_type = "memory";
> + reg = <0x0 0x40000000>; /* 1GB */
> + };
> +
> + soc {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> +&gmac1 {
> + status = "okay";
> + phy-mode = "rgmii";
> +};
> +
> +&gpio0 {
> + status = "okay";
> +};
> +
> +&gpio1 {
> + status = "okay";
> +};
> +
> +&gpio2 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> + speed-mode = <0>;
> +};
> +
> +&i2c1 {
> + status = "okay";
> + speed-mode = <0>;
> +};
> +
> +&mmc0 {
> + status = "okay";
> + bus-width = <8>;
> + u-boot,dm-pre-reloc;
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&usb1 {
> + status = "okay";
> +};
> +
> +&watchdog0 {
> + status = "okay";
> +};
> +
> +&qspi {
> + status = "okay";
> + u-boot,dm-pre-reloc;
> +
> + flash0: n25q00@0 {
> + u-boot,dm-pre-reloc;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "n25q00", "spi-flash";
> + reg = <0>; /* chip select */
> + spi-max-frequency = <50000000>;
> + m25p,fast-read;
> + page-size = <256>;
> + block-size = <16>; /* 2^16, 64KB */
> + read-delay = <4>; /* delay value in read data capture register
*/
> + tshsl-ns = <50>;
> + tsd2d-ns = <50>;
> + tchsh-ns = <4>;
> + tslch-ns = <4>;
> + };
> +};
[...]
> diff --git a/board/sr1500/socfpga.c b/board/sr1500/socfpga.c
> new file mode 100644
> index 0000000..35d68a9
> --- /dev/null
> +++ b/board/sr1500/socfpga.c
> @@ -0,0 +1,151 @@
> +/*
> + * Copyright (C) 2015 Stefan Roese <s...@denx.de>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <i2c.h>
> +#include <miiphy.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void s_init(void) {}
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +int board_init(void)
> +{
> + /* Address of boot parameters for ATAG (if ATAG is used) */
> + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> +
> + return 0;
> +}
> +
> +int board_early_init_f(void)
> +{
> + int ret;
> +
> + /* Reset the Marvell PHY 88E1510 */
> + ret = gpio_request(63, "PHY reset");
> + if (ret)
> + return ret;
> +
> + gpio_direction_output(63, 0);
> + mdelay(10);
> + gpio_set_value(63, 1);
> + mdelay(10);
> +
> + return 0;
> +}
> +
> +#define CONFIG_SYS_IDT_CLK_ADDR 0x6a
> +
> +static int do_clksave(cmd_tbl_t *cmdtp, int flag, int argc, char *const
> argv[]) +{
> + u8 buf[1];
> +
> + buf[0] = 0x01;
> + i2c_write(CONFIG_SYS_IDT_CLK_ADDR, 0, 0, buf, 1);
> +
> + return 0;
> +}
> +
> +U_BOOT_CMD(clksave, 1, 0, do_clksave,
> + "IDT 5V49EE702 Progsave command", "");
> +
> +#define NET_DEV_NAME "ethernet@ff702000"
> +#define MII_MARVELL_PHY_PAGE 22
> +#define PHY_DIAG_START (1 << 15)
> +#define PHY_DIAG_BUSY (1 << 11)
> +#define PHY_DIAG_TIMEOUT 5000 /* 5 seconds */
> +
> +static char *pair_state(int val, char *str)
> +{
> + switch (val) {
> + case 0x00:
> + strcpy(str, "Invalid");
> + break;
> + case 0x01:
> + strcpy(str, "Pair Ok");
> + break;
> + case 0x02:
> + strcpy(str, "Pair Open");
> + break;
> + case 0x03:
> + strcpy(str, "Same Pair Short");
> + break;
> + case 0x04:
> + strcpy(str, "Cross Pair Short");
> + break;
> + case 0x09:
> + strcpy(str, "Pair Busy");
> + break;
> + default:
> + strcpy(str, "Reserved");
> + break;
> + };
> +
> + return str;
> +}
> +
> +static int do_phytest(cmd_tbl_t *cmdtp, int flag, int argc, char *const
> argv[]) +{
> + const char devname[] = NET_DEV_NAME;
> + unsigned long ts;
> + char str[32];
> + u8 addr = 0;
> + u16 data;
> + u16 status;
> + u16 oldpage;
> + int i;
> +
> + /* Save current page register */
> + miiphy_read(devname, addr, MII_MARVELL_PHY_PAGE, &oldpage);
> +
> + /*
> + * Run cable disgnostics
> + */
> + printf("Running cable diagnostic test...");
> + miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, 7);
> + miiphy_write(devname, addr, 21, PHY_DIAG_START);
> +
> + ts = get_timer(0);
> + do {
> + miiphy_read(devname, addr, 21, &data);
> + if ((data & PHY_DIAG_BUSY) != PHY_DIAG_BUSY)
> + break;
> +
> + mdelay(1);
> + } while (get_timer(ts) < PHY_DIAG_TIMEOUT);
> + printf("done!\n");
> +
> + miiphy_read(devname, addr, 20, &status);
> +
> + for (i = 0; i < 4; i++) {
> + int val;
> +
> + val = (status >> (i * 4)) & 0x000f;
> + pair_state(val, str);
> + printf("Pair %d: %s", i, str);
> +
> + /* Only print fault length if not okay */
> + if (val != 0x01) {
> + miiphy_read(devname, addr, 16 + i, &data);
> + printf(" - Length to fault %d cm", data);
> + }
> + printf("\n");
> + }
> +
> + /* Restore original page */
> + miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, oldpage);
> +
> + return 0;
> +}
> +
> +U_BOOT_CMD(phytest, 1, 1, do_phytest,
> + "Marvell PHY test command - dump some values", "");
[...]
Reviewed-by: Marek Vasut <ma...@denx.de>
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