On 10/15/2015 02:14 AM, Prabhakar Kushwaha wrote:
> From: Pratiyush Mohan Srivastava <pratiyush.srivast...@freescale.com>
>
> LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
> personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
>
> So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
>
> Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivast...@freescale.com>
> ---
<snip>
> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
> b/arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
> similarity index 98%
> rename from arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
> rename to arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
> index 0b79a50..64da31c 100644
> --- a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
> +++ b/arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
> @@ -29,7 +29,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
> SGMII1 } },
> {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
> {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
> - {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
> + {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } },
Is this change related for LS2080 only? Does LS2085 use the first four lanes?
With this patch, target LS2080AQDS/RDB will support both LS2080 and LS2085,
correct?
York
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