On Wed, Sep 9, 2015 at 7:52 AM, Simon Glass <s...@chromium.org> wrote:
> Add support for the debug UART on link. This is useful for early debugging.
>
> Signed-off-by: Simon Glass <s...@chromium.org>
> ---
>
> arch/x86/cpu/ivybridge/cpu.c | 7 +++++++
> configs/chromebook_link_defconfig | 10 +++++++---
> 2 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
> index cce5923..0e6512c 100644
> --- a/arch/x86/cpu/ivybridge/cpu.c
> +++ b/arch/x86/cpu/ivybridge/cpu.c
> @@ -340,3 +340,10 @@ int print_cpuinfo(void)
>
> return 0;
> }
> +
> +void board_debug_uart_init(void)
> +{
> + /* This enables the debug UART */
> + pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN,
> + PCI_SIZE_16);
> +}
> diff --git a/configs/chromebook_link_defconfig
> b/configs/chromebook_link_defconfig
> index b3ae925..7408cb1 100644
> --- a/configs/chromebook_link_defconfig
> +++ b/configs/chromebook_link_defconfig
> @@ -15,17 +15,21 @@ CONFIG_CMD_BOOTSTAGE=y
> CONFIG_CMD_TPM=y
> CONFIG_CMD_TPM_TEST=y
> CONFIG_OF_CONTROL=y
> -CONFIG_DM_PCI=y
> -CONFIG_SPI_FLASH=y
> CONFIG_CMD_CROS_EC=y
> CONFIG_CROS_EC=y
> CONFIG_CROS_EC_LPC=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_DM_PCI=y
> +CONFIG_DM_RTC=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_DEBUG_UART_BASE=0x3f8
> +CONFIG_DEBUG_UART_CLOCK=1843200
> +CONFIG_DEBUG_UART_BOARD_INIT=y
> CONFIG_DM_TPM=y
> CONFIG_TPM_TIS_LPC=y
> CONFIG_VIDEO_VESA=y
> CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
> CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
> -CONFIG_DM_RTC=y
> CONFIG_USE_PRIVATE_LIBGCC=y
> CONFIG_SYS_VSNPRINTF=y
> CONFIG_TPM=y
> --
Reviewed-by: Bin Meng <bmeng...@gmail.com>
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