This patch adds the "nandecc" command to switch between the SPEAr600 internal
1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND
chips with a stronger ECC than 1-bit, as on the x600. And to dynamically
switch between both ECC schemes for backwards compatibility.
Signed-off-by: Stefan Roese <s...@denx.de>
Cc: Viresh Kumar <viresh.ku...@linaro.org>
---
arch/arm/cpu/arm926ejs/spear/cpu.c | 34 ++++++++++++++++++++++++++++++
arch/arm/include/asm/arch-spear/spr_misc.h | 1 +
2 files changed, 35 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c
b/arch/arm/cpu/arm926ejs/spear/cpu.c
index e39cdba..be0d14f 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -83,3 +83,37 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH)
+static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ goto usage;
+
+ if (strncmp(argv[1], "hw", 2) == 0) {
+ /* 1-bit HW ECC */
+ printf("Switching to 1-bit HW ECC\n");
+ fsmc_nand_switch_ecc(1);
+ } else if (strncmp(argv[1], "bch4", 2) == 0) {
+ /* 4-bit SW ECC BCH4 */
+ printf("Switching to 4-bit SW ECC (BCH4)\n");
+ fsmc_nand_switch_ecc(4);
+ } else {
+ goto usage;
+ }
+
+ return 0;
+
+usage:
+ printf("Usage: nandecc %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ nandecc, 2, 0, do_switch_ecc,
+ "switch NAND ECC calculation algorithm",
+ "hw|bch4 - Switch between NAND hardware 1-bit HW and"
+ " 4-bit SW BCH\n"
+);
+#endif
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h
b/arch/arm/include/asm/arch-spear/spr_misc.h
index b55026e..6f2e19e 100644
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -253,5 +253,6 @@ struct misc_regs {
#define SOC_SPEAR320 203
extern int get_socrev(void);
+int fsmc_nand_switch_ecc(uint32_t eccstrength);
#endif
--
2.5.1
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