> -----Original Message----- > From: Tom Warren > Sent: Thursday, August 20, 2015 9:20 AM > To: 'Stephen Warren'; Thierry Reding > Cc: Albert Aribaud; u-boot@lists.denx.de; Stephen Warren > Subject: RE: [U-Boot] [PATCH 2/6] ARM: tegra: Implement clk_m > > Stephen/Thierry, > > > -----Original Message----- > > From: Stephen Warren [mailto:swar...@wwwdotorg.org] > > Sent: Thursday, August 20, 2015 7:59 AM > > To: Thierry Reding > > Cc: Albert Aribaud; Tom Warren; u-boot@lists.denx.de; Stephen Warren > > Subject: Re: [U-Boot] [PATCH 2/6] ARM: tegra: Implement clk_m > > > > On 08/20/2015 03:42 AM, Thierry Reding wrote: > > > From: Thierry Reding <tred...@nvidia.com> > > > > > > On currently supported SoCs, clk_m always runs at the same frequency > > > as the oscillator input. However newer SoC generations such as > > > Tegra210 no longer have that restriction. Prepare for that by > > > separating clk_m from the oscillator clock and allow SoC code to > > > override > > the clk_m rate. > > > > > diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h > > > b/arch/arm/include/asm/arch-tegra114/clock-tables.h > > > index d8fa0e1d2cee..3f910f5ae8b9 100644 > > > --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h > > > +++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h > > > @@ -38,6 +38,7 @@ enum clock_id { > > > /* These are the base clocks (inputs to the Tegra SOC) */ > > > CLOCK_ID_32KHZ, > > > CLOCK_ID_OSC, > > > + CLOCK_ID_CLK_M, > > > > > > CLOCK_ID_COUNT, /* number of PLLs */ > > > CLOCK_ID_DISPLAY2, /* placeholder */ > > > > clock.h contains the following: > > > > /* Number of PLL-based clocks (i.e. not OSC or 32KHz) */ > > #define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 2) > > I decremented the CLOCK_ID_COUNT for my pllinfo tables, since 32KHZ and > OSC have no PLL params that can be configured, to remove the 2 extra, > empty table entries. > We can either remove it, and add 2 empty entries for OSC/32KHZ in all the > pllinfo tables (per SoC), and then add new CLOCK_ID entries wherever, or > have a rule that new entries here need to be above ID_32KHZ for any PLL > needing dividers, etc., and below it for any static clock like OSC, 32KHz, > etc. > Of course, we'll need to keep track of the decrement depending on how > many IDs are added and where. Might be easier to just have an entry for > every CLOCK_ID, regardless.
I applied Thierry's patchset and found that adding CLK_M to the CLOCK_ID tables results in an extra empty pll_info_table entry (3 32-bit words) for each SoC. So I can leave it as-is, or I can adjust CLOCK_ID_PLL_COUNT in clock.h to be CLOCK_ID_COUNT - 3 to account for the 3 non-configurable clocks (OSC, 32KHz and MCLK), and there'll be no extra empty data in the pll_info tables. I'm going to go with the 2nd approach. I've applied these (plus some from Stephen and one from Axel Lin) to u-boot-tegra/next and after some testing today I'll be pushing this to Denx for everyone to play with it before I send a PR to TomR. So PTAL. Thanks Tom -- nvpublic > > > > > ... which would need to be updated. Related, see internal bug number > > 1676978 to see if any of the other gotchas there affect this patch. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
