These GPIOs are accessible on the pin header. Add pinctrl settings for them
so that we they can be adjusted using the 'gpio' command.
Signed-off-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
arch/x86/dts/minnowmax.dts | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index f4e0a35..a8ecf0d 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -30,6 +30,33 @@
compatible = "intel,x86-pinctrl";
io-base = <0x4c>;
+ /* GPIO E0 */
+ soc_gpio_s5_0@0 {
+ gpio-offset = <0x80 0>;
+ pad-offset = <0x1d0>;
+ mode-gpio;
+ output-value = <0>;
+ direction = <PIN_OUTPUT>;
+ };
+
+ /* GPIO E1 */
+ soc_gpio_s5_1@0 {
+ gpio-offset = <0x80 1>;
+ pad-offset = <0x210>;
+ mode-gpio;
+ output-value = <0>;
+ direction = <PIN_OUTPUT>;
+ };
+
+ /* GPIO E2 */
+ soc_gpio_s5_2@0 {
+ gpio-offset = <0x80 2>;
+ pad-offset = <0x1e0>;
+ mode-gpio;
+ output-value = <0>;
+ direction = <PIN_OUTPUT>;
+ };
+
pin_usb_host_en0@0 {
gpio-offset = <0x80 8>;
pad-offset = <0x260>;
--
2.5.0.457.gab17608
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