On 30 July 2015 at 11:04, Vignesh R <vigne...@ti.com> wrote:
> From: Kishon Vijay Abraham I <kis...@ti.com>
>
> Add do_disable_clocks() to disable clock domains and module clocks.
> These clocks are enabled using do_enable_clocks().
>
> Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
> Signed-off-by: Vignesh R <vigne...@ti.com>
> ---
Reviewed-by: Jagan Teki <jt...@openedev.com>
> arch/arm/cpu/armv7/omap-common/clocks-common.c | 53
> ++++++++++++++++++++++++++
> arch/arm/include/asm/omap_common.h | 4 ++
> 2 files changed, 57 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c
> b/arch/arm/cpu/armv7/omap-common/clocks-common.c
> index c94a80781931..e28b79568d1d 100644
> --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
> +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
> @@ -648,6 +648,14 @@ static inline void enable_clock_domain(u32 const
> clkctrl_reg, u32 enable_mode)
> debug("Enable clock domain - %x\n", clkctrl_reg);
> }
>
> +static inline void disable_clock_domain(u32 const clkctrl_reg)
> +{
> + clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
> + CD_CLKCTRL_CLKTRCTRL_SW_SLEEP <<
> + CD_CLKCTRL_CLKTRCTRL_SHIFT);
> + debug("Disable clock domain - %x\n", clkctrl_reg);
> +}
> +
> static inline void wait_for_clk_enable(u32 clkctrl_addr)
> {
> u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
> @@ -677,6 +685,34 @@ static inline void enable_clock_module(u32 const
> clkctrl_addr, u32 enable_mode,
> wait_for_clk_enable(clkctrl_addr);
> }
>
> +static inline void wait_for_clk_disable(u32 clkctrl_addr)
> +{
> + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL;
> + u32 bound = LDELAY;
> +
> + while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) {
> + clkctrl = readl(clkctrl_addr);
> + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
> + MODULE_CLKCTRL_IDLEST_SHIFT;
> + if (--bound == 0) {
> + printf("Clock disable failed for 0x%x idlest 0x%x\n",
> + clkctrl_addr, clkctrl);
> + return;
> + }
> + }
> +}
> +
> +static inline void disable_clock_module(u32 const clkctrl_addr,
> + u32 wait_for_disable)
> +{
> + clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
> + MODULE_CLKCTRL_MODULEMODE_SW_DISABLE <<
> + MODULE_CLKCTRL_MODULEMODE_SHIFT);
> + debug("Disable clock module - %x\n", clkctrl_addr);
> + if (wait_for_disable)
> + wait_for_clk_disable(clkctrl_addr);
> +}
> +
> void freq_update_core(void)
> {
> u32 freq_config1 = 0;
> @@ -800,6 +836,23 @@ void do_enable_clocks(u32 const *clk_domains,
> }
> }
>
> +void do_disable_clocks(u32 const *clk_domains,
> + u32 const *clk_modules_disable,
> + u8 wait_for_disable)
> +{
> + u32 i, max = 100;
Why is this 100 max value?
> +
> +
> + /* Clock modules that need to be put in SW_DISABLE */
> + for (i = 0; (i < max) && clk_modules_disable[i]; i++)
> + disable_clock_module(clk_modules_disable[i],
> + wait_for_disable);
> +
> + /* Put the clock domains in SW_SLEEP mode */
> + for (i = 0; (i < max) && clk_domains[i]; i++)
> + disable_clock_domain(clk_domains[i]);
> +}
> +
> void prcm_init(void)
> {
> switch (omap_hw_init_context()) {
> diff --git a/arch/arm/include/asm/omap_common.h
> b/arch/arm/include/asm/omap_common.h
> index 056affc3fabd..87cdaad1d60f 100644
> --- a/arch/arm/include/asm/omap_common.h
> +++ b/arch/arm/include/asm/omap_common.h
> @@ -575,6 +575,10 @@ void do_enable_clocks(u32 const *clk_domains,
> u32 const *clk_modules_explicit_en,
> u8 wait_for_enable);
>
> +void do_disable_clocks(u32 const *clk_domains,
> + u32 const *clk_modules_disable,
> + u8 wait_for_disable);
> +
> void setup_post_dividers(u32 const base,
> const struct dpll_params *params);
> u32 omap_ddr_clk(void);
> --
> 2.5.0
>
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thanks!
--
Jagan | openedev.
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