This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>
---
arch/powerpc/cpu/mpc85xx/Kconfig | 4 -
board/freescale/mpc8548cds/Kconfig | 12 -
board/freescale/mpc8548cds/MAINTAINERS | 8 -
board/freescale/mpc8548cds/Makefile | 12 -
board/freescale/mpc8548cds/ddr.c | 56 ---
board/freescale/mpc8548cds/law.c | 19 -
board/freescale/mpc8548cds/mpc8548cds.c | 358 -------------------
board/freescale/mpc8548cds/tlb.c | 87 -----
configs/MPC8548CDS_36BIT_defconfig | 4 -
configs/MPC8548CDS_defconfig | 3 -
configs/MPC8548CDS_legacy_defconfig | 4 -
include/configs/MPC8548CDS.h | 605 --------------------------------
12 files changed, 1172 deletions(-)
delete mode 100644 board/freescale/mpc8548cds/Kconfig
delete mode 100644 board/freescale/mpc8548cds/MAINTAINERS
delete mode 100644 board/freescale/mpc8548cds/Makefile
delete mode 100644 board/freescale/mpc8548cds/ddr.c
delete mode 100644 board/freescale/mpc8548cds/law.c
delete mode 100644 board/freescale/mpc8548cds/mpc8548cds.c
delete mode 100644 board/freescale/mpc8548cds/tlb.c
delete mode 100644 configs/MPC8548CDS_36BIT_defconfig
delete mode 100644 configs/MPC8548CDS_defconfig
delete mode 100644 configs/MPC8548CDS_legacy_defconfig
delete mode 100644 include/configs/MPC8548CDS.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 1922045..d05f943 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -43,9 +43,6 @@ config TARGET_P5040DS
config TARGET_MPC8536DS
bool "Support MPC8536DS"
-config TARGET_MPC8548CDS
- bool "Support MPC8548CDS"
-
config TARGET_MPC8555CDS
bool "Support MPC8555CDS"
@@ -145,7 +142,6 @@ source "board/freescale/bsc9132qds/Kconfig"
source "board/freescale/c29xpcie/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
source "board/freescale/mpc8536ds/Kconfig"
-source "board/freescale/mpc8548cds/Kconfig"
source "board/freescale/mpc8555cds/Kconfig"
source "board/freescale/mpc8560ads/Kconfig"
source "board/freescale/mpc8568mds/Kconfig"
diff --git a/board/freescale/mpc8548cds/Kconfig
b/board/freescale/mpc8548cds/Kconfig
deleted file mode 100644
index 09f3b0b..0000000
--- a/board/freescale/mpc8548cds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8548CDS
-
-config SYS_BOARD
- default "mpc8548cds"
-
-config SYS_VENDOR
- default "freescale"
-
-config SYS_CONFIG_NAME
- default "MPC8548CDS"
-
-endif
diff --git a/board/freescale/mpc8548cds/MAINTAINERS
b/board/freescale/mpc8548cds/MAINTAINERS
deleted file mode 100644
index 6f22922..0000000
--- a/board/freescale/mpc8548cds/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-MPC8548CDS BOARD
-#M: -
-S: Maintained
-F: board/freescale/mpc8548cds/
-F: include/configs/MPC8548CDS.h
-F: configs/MPC8548CDS_defconfig
-F: configs/MPC8548CDS_36BIT_defconfig
-F: configs/MPC8548CDS_legacy_defconfig
diff --git a/board/freescale/mpc8548cds/Makefile
b/board/freescale/mpc8548cds/Makefile
deleted file mode 100644
index f797df2..0000000
--- a/board/freescale/mpc8548cds/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Copyright 2004 Freescale Semiconductor.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += mpc8548cds.o
-obj-y += ddr.o
-obj-y += law.o
-obj-y += tlb.o
diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c
deleted file mode 100644
index b31ea34..0000000
--- a/board/freescale/mpc8548cds/ddr.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for clock adjust:
- * - number of chips on bus
- * - position of slot
- * - DDR1 vs. DDR2?
- * - ???
- *
- * This needs to be determined on a board-by-board basis.
- * 0110 3/4 cycle late
- * 0111 7/8 cycle late
- */
- popts->clk_adjust = 7;
-
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 10;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
deleted file mode 100644
index 5578fc2..0000000
--- a/board/freescale/mpc8548cds/law.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
- /* LBC window - maps 256M */
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c
b/board/freescale/mpc8548cds/mpc8548cds.c
deleted file mode 100644
index ca9b43c..0000000
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/*
- * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2002 Scott McNutt <smcn...@artesyncp.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <tsec.h>
-#include <fsl_mdio.h>
-#include <netdev.h>
-
-#include "../common/cadmus.h"
-#include "../common/eeprom.h"
-#include "../common/via.h"
-
-void local_bus_init(void);
-
-int checkboard (void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
-
- /* PCI slot in USER bits CSR[6:7] by convention. */
- uint pci_slot = get_pci_slot ();
-
- uint cpu_board_rev = get_cpu_board_revision ();
-
- puts("Board: MPC8548CDS");
- printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
- get_board_version(), pci_slot);
- printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
- MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
- MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
- /*
- * Initialize local bus.
- */
- local_bus_init ();
-
- /*
- * Hack TSEC 3 and 4 IO voltages.
- */
- gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
-
- ecm->eedr = 0xffffffff; /* clear ecm errors */
- ecm->eeer = 0xffffffff; /* enable ecm errors */
- return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void
-local_bus_init(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
- uint clkdiv;
- sys_info_t sysinfo;
-
- get_sys_info(&sysinfo);
- clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
-
- gur->lbiuiplldcr1 = 0x00078080;
- if (clkdiv == 16) {
- gur->lbiuiplldcr0 = 0x7c0f1bf0;
- } else if (clkdiv == 8) {
- gur->lbiuiplldcr0 = 0x6c0f1bf0;
- } else if (clkdiv == 4) {
- gur->lbiuiplldcr0 = 0x5c0f1bf0;
- }
-
- lbc->lcrr |= 0x00030000;
-
- asm("sync;isync;msync");
-
- lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
- lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
-}
-
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-void lbc_sdram_init(void)
-{
-#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-
- uint idx;
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
- uint lsdmr_common;
-
- puts("LBC SDRAM: ");
- print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
- "\n");
-
- /*
- * Setup SDRAM Base and Option Registers
- */
- set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
- set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- asm("msync");
-
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- asm("msync");
-
- /*
- * MPC8548 uses "new" 15-16 style addressing.
- */
- lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
- lsdmr_common |= LSDMR_BSMA1516;
-
- /*
- * Issue PRECHARGE ALL command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue 8 AUTO REFRESH commands.
- */
- for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
- }
-
- /*
- * Issue 8 MODE-set command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(100);
-
- /*
- * Issue NORMAL OP command.
- */
- lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
- asm("sync;msync");
- *sdram_addr = 0xff;
- ppcDcbf((unsigned long) sdram_addr);
- udelay(200); /* Overkill. Must wait > 200 bus cycles */
-
-#endif /* enable SDRAM init */
-}
-
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device. Work around that by refusing to configure it.
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct
pci_config_table *tab) { }
-
-static struct pci_config_table pci_mpc85xxcds_config_table[] = {
- {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
- mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
- mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
- mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
- mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
- mpc85xx_config_via_ac97, {0,0,0}},
- {},
-};
-
-static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI */
-
-void pci_init_board(void)
-{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info;
- u32 devdisr, pordevsr, io_sel;
- u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
- int first_free_busno = 0;
- char buf[32];
-
- devdisr = in_be32(&gur->devdisr);
- pordevsr = in_be32(&gur->pordevsr);
- porpllsr = in_be32(&gur->porpllsr);
- io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
- debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-
-#ifdef CONFIG_PCI1
- pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
- pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15]
*/
- pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
- pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
- if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- SET_STD_PCI_INFO(pci_info, 1);
- set_next_law(pci_info.mem_phys,
- law_size_bits(pci_info.mem_size), pci_info.law);
- set_next_law(pci_info.io_phys,
- law_size_bits(pci_info.io_size), pci_info.law);
-
- pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
- printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
- (pci_32) ? 32 : 64,
- strmhz(buf, pci_speed),
- pci_clk_sel ? "sync" : "async",
- pci_agent ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter",
- pci_info.regs);
-
- pci1_hose.config_table = pci_mpc85xxcds_config_table;
- first_free_busno = fsl_pci_init_port(&pci_info,
- &pci1_hose, first_free_busno);
-
-#ifdef CONFIG_PCIX_CHECK
- if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
- /* PCI-X init */
- if (CONFIG_SYS_CLK_FREQ < 66000000)
- printf("PCI-X will only work at 66 MHz\n");
-
- reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
- | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
- pci_hose_write_config_word(hose, bus, PCIX_COMMAND,
reg16);
- }
-#endif
- } else {
- printf("PCI1: disabled\n");
- }
-
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-
-#ifdef CONFIG_PCI2
-{
- uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
- uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
- if (pci_dual) {
- printf("PCI2: 32 bit, 66 MHz, %s\n",
- pci2_clk_sel ? "sync" : "async");
- } else {
- printf("PCI2: disabled\n");
- }
-}
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
-#endif /* CONFIG_PCI2 */
-
- fsl_pcie_init_board(first_free_busno);
-}
-
-void configure_rgmii(void)
-{
- unsigned short temp;
-
- /* Change the resistors for the PHY */
- /* This is needed to get the RGMII working for the 1.3+
- * CDS cards */
- if (get_board_version() == 0x13) {
- miiphy_write(DEFAULT_MII_NAME,
- TSEC1_PHY_ADDR, 29, 18);
-
- miiphy_read(DEFAULT_MII_NAME,
- TSEC1_PHY_ADDR, 30, &temp);
-
- temp = (temp & 0xf03f);
- temp |= 2 << 9; /* 36 ohm */
- temp |= 2 << 6; /* 39 ohm */
-
- miiphy_write(DEFAULT_MII_NAME,
- TSEC1_PHY_ADDR, 30, temp);
-
- miiphy_write(DEFAULT_MII_NAME,
- TSEC1_PHY_ADDR, 29, 3);
-
- miiphy_write(DEFAULT_MII_NAME,
- TSEC1_PHY_ADDR, 30, 0x8000);
- }
-
- return;
-}
-
-#ifdef CONFIG_TSEC_ENET
-int board_eth_init(bd_t *bis)
-{
- struct fsl_pq_mdio_info mdio_info;
- struct tsec_info_struct tsec_info[4];
- int num = 0;
-
-#ifdef CONFIG_TSEC1
- SET_STD_TSEC_INFO(tsec_info[num], 1);
- num++;
-#endif
-#ifdef CONFIG_TSEC2
- SET_STD_TSEC_INFO(tsec_info[num], 2);
- num++;
-#endif
-#ifdef CONFIG_TSEC3
- /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
- if (get_board_version() >= 0x13) {
- SET_STD_TSEC_INFO(tsec_info[num], 3);
- tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
- num++;
- }
-#endif
-#ifdef CONFIG_TSEC4
- /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
- if (get_board_version() >= 0x13) {
- SET_STD_TSEC_INFO(tsec_info[num], 4);
- tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
- num++;
- }
-#endif
-
- if (!num) {
- printf("No TSECs initialized\n");
-
- return 0;
- }
-
- mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
- mdio_info.name = DEFAULT_MII_NAME;
- fsl_pq_mdio_init(bis, &mdio_info);
-
- tsec_eth_init(bis, tsec_info, num);
- configure_rgmii();
-
- return pci_eth_init(bis);
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_pci_setup(void *blob, bd_t *bd)
-{
- FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
deleted file mode 100644
index 363e043..0000000
--- a/board/freescale/mpc8548cds/tlb.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright 2008, 2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- /* TLB 0 - for temp stack in cache */
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
- /* TLB 1 */
- /*
- * Entry 0:
- * FLASH(cover boot page) 16M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
-
- /*
- * Entry 1:
- * CCSRBAR 1M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- /*
- * Entry 2:
- * LBC SDRAM 64M Cacheable, non-guarded
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
- CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 2, BOOKE_PAGESZ_64M, 1),
-
- /*
- * Entry 3:
- * CADMUS registers 1M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1M, 1),
-
- /*
- * Entry 4:
- * PCI and PCIe MEM 1G Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_1G, 1),
-
- /*
- * Entry 5:
- * PCI1 IO 1M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_1M, 1),
-
- /*
- * Entry 6:
- * PCIe IO 1M Non-cacheable, guarded
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
- MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_1M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/MPC8548CDS_36BIT_defconfig
b/configs/MPC8548CDS_36BIT_defconfig
deleted file mode 100644
index dfe1fca..0000000
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_MPC8548CDS=y
-CONFIG_SYS_EXTRA_OPTIONS="36BIT"
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
deleted file mode 100644
index ba52e94..0000000
--- a/configs/MPC8548CDS_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_MPC8548CDS=y
diff --git a/configs/MPC8548CDS_legacy_defconfig
b/configs/MPC8548CDS_legacy_defconfig
deleted file mode 100644
index 69c44af..0000000
--- a/configs/MPC8548CDS_legacy_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_MPC8548CDS=y
-CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
deleted file mode 100644
index a80221a..0000000
--- a/include/configs/MPC8548CDS.h
+++ /dev/null
@@ -1,605 +0,0 @@
-/*
- * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * mpc8548cds board configuration file
- *
- * Please refer to doc/README.mpc85xxcds for more info.
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_36BIT
-#define CONFIG_PHYS_64BIT
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC8548 1 /* MPC8548 specific */
-#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xfff80000
-#endif
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-
-#define CONFIG_PCI /* enable any pci type devices */
-#define CONFIG_PCI1 /* PCI controller 1 */
-#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
-#undef CONFIG_PCI2
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
-#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
-#define CONFIG_FSL_VIA
-
-#ifndef __ASSEMBLY__
-extern unsigned long get_clock_freq(void);
-#endif
-#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS 1
-
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1
entries */
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00400000
-
-#define CONFIG_SYS_CCSRBAR 0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SYS_FSL_DDR2
-#undef CONFIG_FSL_DDR_INTERACTIVE
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
-#define CONFIG_DDR_SPD
-
-#define CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system
memory*/
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-/* Make sure required options are set */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ
-/*
- * Physical Address Map
- *
- * 32bit:
- * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
- * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
- * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
- * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
- * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
- * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
- * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
- *
- * 36bit:
- * 0x00000_0000 0x07fff_ffff DDR 2G
cacheable
- * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M
cacheable
- * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M
cacheable
- * 0xc4000_0000 0xc5fff_ffff RapidIO 512M
cacheable
- * 0xfe000_0000 0xfe00f_ffff CCSR 1M
non-cacheable
- * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M
non-cacheable
- * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M
non-cacheable
- * 0xff000_0000 0xff3ff_ffff SDRAM 64M
cacheable
- * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M
non-cacheable
- * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M
non-cacheable
- * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M
non-cacheable
- *
- */
-
-
-/*
- * Local Bus Definitions
- */
-
-/*
- * FLASH on the Local Bus
- * Two banks, 8M each, using the CFI driver.
- * Boot from BR0/OR0 bank at 0xff00_0000
- * Alternate BR1/OR1 bank at 0xff80_0000
- *
- * BR0, BR1:
- * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
- * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
- * Port Size = 16 bits = BRx[19:20] = 10
- * Use GPCM = BRx[24:26] = 000
- * Valid = BRx[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
- * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
- *
- * OR0, OR1:
- * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
- * Reserved ORx[17:18] = 11, confusion here?
- * CSNT = ORx[20] = 1
- * ACS = half cycle delay = ORx[21:22] = 11
- * SCY = 6 = ORx[24:27] = 0110
- * TRLX = use relaxed timing = ORx[29] = 1
- * EAD = use external address latch delay = OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
- */
-
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
-#else
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-#endif
-
-#define CONFIG_SYS_BR0_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_BR1_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
-
-#define CONFIG_SYS_OR0_PRELIM 0xff806e65
-#define CONFIG_SYS_OR1_PRELIM 0xff806e65
-
-#define CONFIG_SYS_FLASH_BANKS_LIST \
- {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of
monitor */
-
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_HWCONFIG /* enable hwconfig */
-
-/*
- * SDRAM on the Local Bus
- */
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
-#else
-#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
-#endif
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
- *
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
- * FIXME: the top 17 bits of BR2.
- */
-
-#define CONFIG_SYS_BR2_PRELIM \
- (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
- | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
-#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh
timer */
-#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer
prescal*/
-
-/*
- * Common settings for all Local Bus SDRAM commands.
- * At run time, either BSMA1516 (for CPU 1.1)
- * or BSMA1617 (for CPU 1.0) (old)
- * is OR'ed in too.
- */
-#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
- | LSDMR_PRETOACT7 \
- | LSDMR_ACTTORW7 \
- | LSDMR_BL8 \
- | LSDMR_WRC4 \
- | LSDMR_CL3 \
- | LSDMR_RFEN \
- )
-
-/*
- * The CADMUS registers are connected to CS3 on CDS.
- * The new memory map places CADMUS at 0xf8000000.
- *
- * For BR3, need:
- * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
- * port-size = 8-bits = BR[19:20] = 01
- * no parity checking = BR[21:22] = 00
- * GPMC for MSEL = BR[24:26] = 000
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
- *
- * For OR3, need:
- * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
- * disable buffer ctrl OR[19] = 0
- * CSNT OR[20] = 1
- * ACS OR[21:22] = 11
- * XACS OR[23] = 1
- * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
- * SETA OR[28] = 0
- * TRLX OR[29] = 1
- * EHTR OR[30] = 1
- * EAD extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
- */
-
-#define CONFIG_FSL_CADMUS
-
-#define CADMUS_BASE_ADDR 0xf8000000
-#ifdef CONFIG_PHYS_64BIT
-#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
-#else
-#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
-#endif
-#define CONFIG_SYS_BR3_PRELIM \
- (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address
*/
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in
RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -
GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon
*/
-#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/*
- * I2C
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/* EEPROM */
-#define CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_CCID
-#define CONFIG_SYS_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
-#else
-#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
-#endif
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
-#else
-#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#endif
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_NAME "Slot"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
-#else
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
-#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
-#endif
-
-/*
- * RapidIO MMU
- */
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
-#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
-#endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
-
-#ifdef CONFIG_LEGACY
-#define BRIDGE_ID 17
-#define VIA_ID 2
-#else
-#define BRIDGE_ID 28
-#define VIA_ID 4
-#endif
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
-#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-
-#endif /* CONFIG_PCI */
-
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "eTSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "eTSEC1"
-#define CONFIG_TSEC3 1
-#define CONFIG_TSEC3_NAME "eTSEC2"
-#define CONFIG_TSEC4
-#define CONFIG_TSEC4_NAME "eTSEC3"
-#undef CONFIG_MPC85XX_FEC
-
-#define CONFIG_PHY_MARVELL
-
-#define TSEC1_PHY_ADDR 0
-#define TSEC2_PHY_ADDR 1
-#define TSEC3_PHY_ADDR 2
-#define TSEC4_PHY_ADDR 3
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-#define TSEC4_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-/* Options are: eTSEC[0-3] */
-#define CONFIG_ETHPRIME "eTSEC0"
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex
detection */
-#endif /* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */
-#define CONFIG_ENV_SIZE 0x2000
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /*
Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer
Size */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for
Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_HAS_ETH3
-#endif
-
-#define CONFIG_IPADDR 192.168.1.253
-
-#define CONFIG_HOSTNAME unknown
-#define CONFIG_ROOTPATH "/nfsroot"
-#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
-#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
-
-#define CONFIG_SERVERIP 192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
-
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ecc=off\0" \
- "netdev=eth0\0" \
- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "consoledev=ttyS1\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=mpc8548cds.dtb\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
--
1.9.1
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