Intel FSP has the capability to walk through the microcode blocks
which are passed as the TempRamInit() parameter from U-Boot and
finds the most appropriate microcode which is suitable for the cpu
on which it is running. Now we've seen several steppings for Intel
BayTrail series processors, adding those microcodes to the Intel
BayleyBay and MinnowMax board device tree files.
Signed-off-by: Bin Meng <bmeng...@gmail.com>
---
arch/x86/dts/bayleybay.dts | 2 ++
arch/x86/dts/minnowmax.dts | 1 +
2 files changed, 3 insertions(+)
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index ea27537..bceef60 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -235,6 +235,8 @@
data = <
#include "microcode/m0230671117.dtsi"
+#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130679901.dtsi"
>;
};
};
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 5711510..2af67e4 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -198,6 +198,7 @@
data = <
#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130679901.dtsi"
>;
};
};
--
1.8.2.1
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