Hi Simon,
On Tue, Jul 28, 2015 at 5:47 AM, Simon Glass <s...@chromium.org> wrote:
> Move this config option to Kconfig and tidy up.
>
> Signed-off-by: Simon Glass <s...@chromium.org>
> ---
Reviewed-by: Bin Meng <bmeng...@gmail.com>
But please see nits below.
>
> configs/efi-x86_defconfig | 1 +
This has dependencies to the efi series. I think we should remove this
change if we apply this series first.
> drivers/serial/Kconfig | 10 ++++++++++
> include/configs/crownbay.h | 1 -
> include/configs/galileo.h | 2 --
> include/configs/minnowmax.h | 1 -
> include/configs/qemu-x86.h | 2 --
> include/configs/x86-chromebook.h | 2 --
> 7 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
> index f07305c..199f320 100644
> --- a/configs/efi-x86_defconfig
> +++ b/configs/efi-x86_defconfig
> @@ -14,3 +14,4 @@ CONFIG_DEBUG_UART_BASE=0
> CONFIG_DEBUG_UART_CLOCK=0
> # CONFIG_CMD_NET is not set
> # CONFIG_CMD_BOOTM is not set
> +# CONFIG_X86_SERIAL is not set
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index f874837..773075b 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -110,3 +110,13 @@ config UNIPHIER_SERIAL
> help
> If you have a UniPhier based board and want to use the on-chip
> serial ports, say Y to this option. If unsure, say N.
> +
> +config X86_SERIAL
> + bool "Support for 16550 serial port on x86 machines"
> + depends on X86
> + default y
> + help
> + Most x86 machines have a ns16550 UART or compatible. This can be
> + enabled in the device tree with the correct input clock frequency
> + provided (default 1843200). Enable this to obtain serial console
> + output.
> diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
> index 6cf53a3..1ea320b 100644
> --- a/include/configs/crownbay.h
> +++ b/include/configs/crownbay.h
> @@ -17,7 +17,6 @@
> #define CONFIG_BOARD_EARLY_INIT_F
> #define CONFIG_ARCH_MISC_INIT
>
> -#define CONFIG_X86_SERIAL
> #define CONFIG_SMSC_LPC47M
>
> #define CONFIG_PCI_MEM_BUS 0x40000000
> diff --git a/include/configs/galileo.h b/include/configs/galileo.h
> index fd89bf3..3c3c6e9 100644
> --- a/include/configs/galileo.h
> +++ b/include/configs/galileo.h
> @@ -17,8 +17,6 @@
> #define CONFIG_BOARD_EARLY_INIT_F
> #define CONFIG_ARCH_MISC_INIT
>
> -#define CONFIG_X86_SERIAL
> -
> /* ns16550 UART is memory-mapped in Quark SoC */
> #undef CONFIG_SYS_NS16550_PORT_MAPPED
>
> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
> index 4781e79..6dad2b1 100644
> --- a/include/configs/minnowmax.h
> +++ b/include/configs/minnowmax.h
> @@ -17,7 +17,6 @@
> #define CONFIG_BOARD_EARLY_INIT_F
> #define CONFIG_ARCH_EARLY_INIT_R
>
> -#define CONFIG_X86_SERIAL
> #define CONFIG_SMSC_LPC47M
>
> #define CONFIG_PCI_MEM_BUS 0xd0000000
> diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
> index 78c296f..c25e331 100644
> --- a/include/configs/qemu-x86.h
> +++ b/include/configs/qemu-x86.h
> @@ -16,8 +16,6 @@
> #define CONFIG_SYS_MONITOR_LEN (1 << 20)
> #define CONFIG_ARCH_MISC_INIT
>
> -#define CONFIG_X86_SERIAL
> -
> #define CONFIG_PCI_MEM_BUS 0xc0000000
> #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
> #define CONFIG_PCI_MEM_SIZE 0x10000000
> diff --git a/include/configs/x86-chromebook.h
> b/include/configs/x86-chromebook.h
> index e8f0bac..d5dd619 100644
> --- a/include/configs/x86-chromebook.h
> +++ b/include/configs/x86-chromebook.h
> @@ -17,8 +17,6 @@
> #define CONFIG_X86_MRC_ADDR 0xfffa0000
> #define CONFIG_CACHE_MRC_SIZE_KB 512
>
> -#define CONFIG_X86_SERIAL
> -
> #define CONFIG_SCSI_DEV_LIST \
> {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
> {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
> --
Regards,
Bin
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