Heiko, this patch is no longer valid since I already posted v2.
But your comments are correct ... Will wait for WD's comments and send v3. Regards, André On Fri, 2009-07-17 at 16:15 +0200, Heiko Schocher wrote: > Hello André, > > André Schwarz wrote: > > This patch fixes DDR-II settings and adds I2C support. > > > > > > Signed-off-by: André Schwarz <andre.schw...@matrix-vision.de> > > --- > > > > include/configs/MVBLM7.h | 48 > > ++++++++++++++++++++------------------------- > > 1 files changed, 21 insertions(+), 27 deletions(-) > > > > diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h > > index ac8cb57..6e347e8 100644 > > --- a/include/configs/MVBLM7.h > > +++ b/include/configs/MVBLM7.h > > @@ -47,12 +47,14 @@ > > #define CONFIG_MPC8XXX_SPI > > #define CONFIG_HARD_SPI > > #define MVBLM7_MMC_CS 0x04000000 > > +#define CONFIG_MISC_INIT_R > > So misc_init_r () gets called, but I didn;t find this in your > patch? May I miss something ... It's included in the other "common code" patch. > > > /* I2C */ > > #undef CONFIG_SOFT_I2C > > > > please add #define CONFIG_HARD_I2C, without, I think, this never > works. ok. > > > #define CONFIG_FSL_I2C > > #define CONFIG_I2C_MULTI_BUS > > +#define CONFIG_I2C_CMD_TREE > > no longer needed. ok. > > > #define CONFIG_SYS_I2C_OFFSET 0x3000 > > #define CONFIG_SYS_I2C2_OFFSET 0x3100 > > > > @@ -62,44 +64,36 @@ > > /* > > * DDR Setup > > */ > > +#undef CONFIG_SPD_EEPROM > > + > > #define CONFIG_SYS_DDR_BASE 0x00000000 > > #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE > > #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE > > #define CONFIG_SYS_83XX_DDR_USES_CS0 1 > > #define CONFIG_SYS_MEMTEST_START (60<<20) > > #define CONFIG_SYS_MEMTEST_END (70<<20) > > +#define CONFIG_VERY_BIG_RAM > > > > -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ > > - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 > > - > > -#define CONFIG_SYS_DDR_SIZE 256 > > +#define CONFIG_SYS_DDRCDR 0x22000001 > > +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 > > > > -/* HC, 75Ohm, DDR-II, DRQ */ > > -#define CONFIG_SYS_DDRCDR 0x80000001 > > -/* EN, ODT_WR, 3BA, 14row, 10col */ > > -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102 > > -#define CONFIG_SYS_DDR_CS1_CONFIG 0x0 > > -#define CONFIG_SYS_DDR_CS2_CONFIG 0x0 > > -#define CONFIG_SYS_DDR_CS3_CONFIG 0x0 > > +#define CONFIG_SYS_DDR_SIZE 512 > > > > -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f > > -#define CONFIG_SYS_DDR_CS1_BNDS 0x0 > > -#define CONFIG_SYS_DDR_CS2_BNDS 0x0 > > -#define CONFIG_SYS_DDR_CS3_BNDS 0x0 > > +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 > > > > -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 > > +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f > > > > -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 > > -#define CONFIG_SYS_DDR_TIMING_1 0x2625b221 > > -#define CONFIG_SYS_DDR_TIMING_2 0x1f9820c7 > > -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 > > +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 > > +#define CONFIG_SYS_DDR_TIMING_1 0x3837c322 > > +#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6 > > +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 > > > > -/* ~MEM_EN, SREN, DDR-II, 32_BE */ > > -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000 > > +#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008 > > #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 > > -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 > > +#define CONFIG_SYS_DDR_INTERVAL 0x02000100 > > > > -#define CONFIG_SYS_DDR_MODE 0x078e0232 > > +#define CONFIG_SYS_DDR_MODE 0x04040242 > > +#define CONFIG_SYS_DDR_MODE2 0x00800000 > > > > /* Flash */ > > #define CONFIG_SYS_FLASH_CFI > > @@ -405,8 +399,8 @@ > > > > #define MV_CI mvBL-M7 > > #define MV_VCI mvBL-M7 > > -#define MV_FPGA_DATA 0xfff80000 > > -#define MV_FPGA_SIZE 0x00076ca2 > > +#define MV_FPGA_DATA 0xfff40000 > > +#define MV_FPGA_SIZE 0 > > #define MV_KERNEL_ADDR 0xff810000 > > #define MV_INITRD_ADDR 0xffb00000 > > #define MV_SOURCE_ADDR 0xff804000 > > @@ -453,7 +447,7 @@ > > "static_ipaddr=192.168.90.10\0" \ > > "static_netmask=255.255.255.0\0" \ > > "static_gateway=0.0.0.0\0" \ > > - "initrd_name=uInitrd.mvblm7-xenorfs\0" \ > > + "initrd_name=uInitrd.mvBL-M7-rfs\0" \ > > "zcip=no\0" \ > > "netboot=yes\0" \ > > "mvtest=Ff\0" \ > > > > > > > > MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler > > Registergericht: Amtsgericht Stuttgart, HRB 271090 > > Geschiaeftsf�hrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, > > Hans-Joachim Reich > > > > > > ------------------------------------------------------------------------ > > > > _______________________________________________ > > U-Boot mailing list > > U-Boot@lists.denx.de > > http://lists.denx.de/mailman/listinfo/u-boot > > bye > Heiko MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschiaeftsf�hrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich
_______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
