This adds dcache support for dwc2. The DMA buffers must be DMA aligned and
is flushed for outgoing transactions before starting transfer. For
ingoing transactions it is invalidated after the transfer has finished.
Signed-off-by: Alexander Stein <alexander...@web.de>
---
drivers/usb/host/dwc2.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index eee60a2..03fba8f 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -22,8 +22,8 @@
#define DWC2_DATA_BUF_SIZE (64 * 1024)
/* We need doubleword-aligned buffers for DMA transfers */
-DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE, 8);
-DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE, 8);
+DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer, DWC2_DATA_BUF_SIZE,
ARCH_DMA_MINALIGN);
+DEFINE_ALIGN_BUFFER(uint8_t, status_buffer, DWC2_STATUS_BUF_SIZE,
ARCH_DMA_MINALIGN);
#define MAX_DEVICE 16
#define MAX_ENDPOINT 16
@@ -802,9 +802,14 @@ int chunk_msg(struct usb_device *dev, unsigned long pipe,
int *pid, int in,
(*pid << DWC2_HCTSIZ_PID_OFFSET),
&hc_regs->hctsiz);
- if (!in)
+ if (!in) {
memcpy(aligned_buffer, (char *)buffer + done, len);
+ flush_dcache_range((unsigned long)aligned_buffer,
+ (unsigned long)((void *)aligned_buffer +
+ roundup(len, ARCH_DMA_MINALIGN)));
+ }
+
writel(phys_to_bus((unsigned long)aligned_buffer),
&hc_regs->hcdma);
@@ -820,6 +825,11 @@ int chunk_msg(struct usb_device *dev, unsigned long pipe,
int *pid, int in,
if (in) {
xfer_len -= sub;
+
+ invalidate_dcache_range((unsigned long)aligned_buffer,
+ (unsigned long)((void *)aligned_buffer +
+ roundup(xfer_len, ARCH_DMA_MINALIGN)));
+
memcpy(buffer + done, aligned_buffer, xfer_len);
if (sub)
stop_transfer = 1;
--
2.4.6
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