Signed-off-by: Vikas Manocha <vikas.mano...@st.com> --- drivers/spi/cadence_qspi_apb.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 313f6ac..515d88e 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -467,6 +467,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) /* Indirect mode configurations */ writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); + writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Disable all interrupts */ writel(0, plat->regbase + CQSPI_REG_IRQMASK); @@ -626,9 +627,6 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, /* for normal read (only ramtron as of now) */ addr_bytes = cmdlen - 1; - /* Setup the indirect trigger address */ - writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); - /* Configure the opcode */ rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB; @@ -723,8 +721,6 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, cmdlen, (unsigned int)cmdbuf); return -EINVAL; } - /* Setup the indirect trigger address */ - writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB; -- 1.7.9.5 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot