The mv881116 PHY initialization is split out to a common file to enable
code reuse between different boards.

Signed-off-by: Simon Kagstrom <simon.kagst...@netinsight.net>
---
 board/Marvell/sheevaplug/sheevaplug.c |   32 +--------------
 board/Marvell/sheevaplug/sheevaplug.h |    8 ----
 drivers/net/phy/Makefile              |    1 +
 drivers/net/phy/mv88e1116.c           |   66 +++++++++++++++++++++++++++++++++
 include/configs/sheevaplug.h          |    1 +
 include/mv88e1116.h                   |   29 ++++++++++++++
 6 files changed, 100 insertions(+), 37 deletions(-)
 create mode 100644 drivers/net/phy/mv88e1116.c
 create mode 100644 include/mv88e1116.h

diff --git a/board/Marvell/sheevaplug/sheevaplug.c 
b/board/Marvell/sheevaplug/sheevaplug.c
index 547126a..2bbbb7a 100644
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -27,6 +27,7 @@
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
 #include "sheevaplug.h"
+#include <mv88e1116.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -120,36 +121,9 @@ int dram_init(void)
 }
 
 #ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
 void reset_phy(void)
 {
-       u16 reg;
-       u16 devadr;
-       char *name = "egiga0";
-
-       if (miiphy_set_current_dev(name))
-               return;
-
-       /* command to read PHY dev address */
-       if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
-               printf("Err..%s could not read PHY dev address\n",
-                       __FUNCTION__);
-               return;
-       }
-
-       /*
-        * Enable RGMII delay on Tx and Rx for CPU port
-        * Ref: sec 4.7.2 of chip datasheet
-        */
-       miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
-       miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
-       reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
-       miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
-       miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
-       /* reset the phy */
-       miiphy_reset(name, devadr);
-
-       printf("88E1116 Initialized on %s\n", name);
+       /* Configure and enable MV88E1116 PHY */
+       mv881116_reset_phy("egiga0");
 }
 #endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/sheevaplug/sheevaplug.h 
b/board/Marvell/sheevaplug/sheevaplug.h
index 3ed5b7f..030d64f 100644
--- a/board/Marvell/sheevaplug/sheevaplug.h
+++ b/board/Marvell/sheevaplug/sheevaplug.h
@@ -30,12 +30,4 @@
 #define SHEEVAPLUG_OE_VAL_LOW          (1 << 29)       /* USB_PWEN low */
 #define SHEEVAPLUG_OE_VAL_HIGH         (1 << 17)       /* LED pin high */
 
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG                10
-#define MV88E1116_CPRSP_CR3_REG                21
-#define MV88E1116_MAC_CTRL_REG         21
-#define MV88E1116_PGADR_REG            22
-#define MV88E1116_RGMII_TXTM_CTRL      (1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL      (1 << 5)
-
 #endif /* __SHEEVAPLUG_H */
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 3b92614..c6bb894 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -27,6 +27,7 @@ LIB   := $(obj)libphy.a
 
 COBJS-$(CONFIG_BITBANGMII) += miiphybb.o
 COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o
+COBJS-$(CONFIG_MV88E1116) += mv88e1116.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/drivers/net/phy/mv88e1116.c b/drivers/net/phy/mv88e1116.c
new file mode 100644
index 0000000..37225f3
--- /dev/null
+++ b/drivers/net/phy/mv88e1116.c
@@ -0,0 +1,66 @@
+/*
+ * Moved from sheevaplug.c:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafu...@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+#include <common.h>
+#include <miiphy.h>
+#include "mv881116.h"
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG                10
+#define MV88E1116_CPRSP_CR3_REG                21
+#define MV88E1116_MAC_CTRL_REG         21
+#define MV88E1116_PGADR_REG            22
+#define MV88E1116_RGMII_TXTM_CTRL      (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL      (1 << 5)
+
+void mv881116_reset_phy(char *name)
+{
+       u16 reg;
+       u16 devadr;
+
+       if (miiphy_set_current_dev(name))
+               return;
+
+       /* command to read PHY dev address */
+       if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+               printf("Err..%s could not read PHY dev address\n",
+                       __FUNCTION__);
+               return;
+       }
+
+       /*
+        * Enable RGMII delay on Tx and Rx for CPU port
+        * Ref: sec 4.7.2 of chip datasheet
+        */
+       miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+       miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+       reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+       miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+       miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+       /* reset the phy */
+       miiphy_reset(name, devadr);
+
+       printf("88E1116 Initialized on %s\n", name);
+}
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index cdd7acd..0acc50c 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -44,6 +44,7 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
 #define CONFIG_KIRKWOOD_EGIGA_INIT     /* Enable GbePort0/1 for kernel */
 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8  /* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_MV88E1116               /* Support for the MV88E1116 PHY */
 
 /*
  * CLKs configurations
diff --git a/include/mv88e1116.h b/include/mv88e1116.h
new file mode 100644
index 0000000..6495ae8
--- /dev/null
+++ b/include/mv88e1116.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagst...@netinsight.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+#ifndef __MV881116_H
+#define __MV881116_H
+
+void mv881116_reset_phy(char *name);
+
+#endif /* __MV881116_H */
-- 
1.6.0.4

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