On Mon, Jul 6, 2009 at 7:07 PM, Alemao<xcarand...@gmail.com> wrote: > On Mon, Jul 6, 2009 at 3:45 PM, Scott Wood<scottw...@freescale.com> wrote: >> On Mon, Jul 06, 2009 at 02:39:26PM -0300, Alemao wrote: >>> Hi all, >>> >>> I've made ports of u-boot for two powerpc processors, MPC8343 and >>> MPC8541. >>> >>> The boards has 128MB of DDR2. So I enabled CFG_DRAM_TEST in 127MB >>> of those memories, and I got two scenarios: >>> >>> MPC8343(ddr_clk = 264 MHz): test tooks 1min 35sec >>> >>> MPC8541(ddr_clk = 333 MHz): test tooks 5 sec >>> >>> Note: memories get ddr_clk / 2 >>> >>> Make sense? >>> Is this cause MPC85xx family has L2 cache? >>> Or cause ddr_clk? Or my port has problems in DDR configuration? >>> >>> Im using Micron DDR2 memory, MT47H32M16HR-3:F, with CL = 3 for both ports. >> >> I believe data cache is disabled on 83xx in u-boot. >> >> -Scott >> > > So the time for MPC8343 makes sense??? It tooks that long? > > Data cache/instruction cache is inside e300c1 core, u-boot still have > to enable/support it? > > Any hint how could I do it in 83xx family? > > Im loosing a lot of performance and all boards needs to pass this test > before goes out... > > Cheers, > > -- > Alemao >
I forgot to mention that Im running dram test already in ram. So it's faster then run it from flash. -- Alemao _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
