Freescale PCIe controllers v3.0 and later need to set bit
CFG_READY to allow all inbound configuration transactions
to be processed normally when in EP mode. However, bit
CFG_READY has been moved from PCIe configuration space to
CCSR PCIe configuration register comparing previous version.
The patch is to set this bit according to PCIe version.
Signed-off-by: Ed Swarthout <ed.swarth...@freescale.com>
Signed-off-by: Roy Zang <tie-fei.z...@freescale.com>
Signed-off-by: Minghuan Lian <minghuan.l...@freescale.com>
---
arch/powerpc/include/asm/fsl_pci.h | 1 +
drivers/pci/fsl_pci_init.c | 8 +++++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h
b/arch/powerpc/include/asm/fsl_pci.h
index 5be718b..8bee8ca 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -19,6 +19,7 @@
#define FSL_PCI_PBFR 0x44
#define FSL_PCIE_CFG_RDY 0x4b0
+#define FSL_PCIE_V3_CFG_RDY 0x1
#define FSL_PROG_IF_AGENT 0x1
#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 231b075..1143178 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -682,8 +682,14 @@ void fsl_pci_config_unlock(struct pci_controller *hose)
pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
if (pcie_cap != 0x0) {
+ ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
+ u32 block_rev = in_be32(&pci->block_rev1);
/* PCIe - set CFG_READY bit of Configuration Ready Register */
- pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
+ if (block_rev >= PEX_IP_BLK_REV_3_0)
+ setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
+ else
+ pci_hose_write_config_byte(hose, dev,
+ FSL_PCIE_CFG_RDY, 0x1);
} else {
/* PCI - clear ACL bit of PBFR */
pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
--
1.9.1
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