On Mon, Mar 09, 2015 at 05:12:06PM -0500, Nishanth Menon wrote:

> From: Praveen Rao <p...@ti.com>
> 
> This patch enables the workaround for ARM errata 798870 for OMAP5 /
> DRA7 which says "If back-to-back speculative cache line fills (fill
> A and fill B) are issued from the L1 data cache of a CPU to the
> L2 cache, the second request (fill B) is then cancelled, and the
> second request would have detected a hazard against a recent write or
> eviction (write B) to the same cache line as fill B then the L2 logic
> might deadlock."
> 
> An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced
> here as well.
> 
> Signed-off-by: Praveen Rao <p...@ti.com>
> Signed-off-by: Angela Stegmaier <angelaba...@ti.com>
> Signed-off-by: Nishanth Menon <n...@ti.com>

Reviewed-by: Tom Rini <tr...@konsulko.com>

-- 
Tom

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