Helper function for SoCs which use Cortex A7 cpu cores, this should be called
by the SoC's soc_init function to properly setup the cpu core before calling
cpu_init_cp15.
Signed-off-by: Hans de Goede <hdego...@redhat.com>
---
arch/arm/cpu/armv7/start.S | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 9882b20..f53e5ef 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -182,6 +182,23 @@ ENTRY(cpu_init_cp15)
mov pc, lr @ back to my caller
ENDPROC(cpu_init_cp15)
+/*************************************************************************
+ *
+ * cpu_init_cortex_a7
+ *
+ * Set the ACTLR.SMP bit. "Cortex-A7 MPCore Technical Reference Manual":
+ * "You must ensure this bit is set to 1 before the caches and MMU are
+ * enabled, or any cache and TLB maintenance operations are performed."
+ * So for cortex A7 this must be called before calling cpu_init_cp15.
+ *
+ *************************************************************************/
+ENTRY(cpu_init_cortex_a7)
+ mrc p15, 0, r0, c1, c0, 1
+ orr r0, r0, #(1<<6)
+ mcr p15, 0, r0, c1, c0, 1
+ mov pc, lr @ back to my caller
+ENDPROC(cpu_init_cortex_a7)
+
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*************************************************************************
*
--
2.1.0
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