On some SoCs / ARMv7 CPU cores we need to do some setup before enabling the
icache, etc. Add a soc_init hook with a weak default which just calls
cpu_init_cp15.
This way different implementations can be provided to do some extra work
before or after cpu_init_cp15, or completely replacing cpu_init_cp15.
Signed-off-by: Hans de Goede <hdego...@redhat.com>
---
arch/arm/cpu/armv7/start.S | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index fdc05b9..9882b20 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -64,7 +64,7 @@ reset:
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_cp15
+ bl soc_init
bl cpu_init_crit
#endif
@@ -102,6 +102,22 @@ ENDPROC(save_boot_params)
/*************************************************************************
*
+ * void soc_init(void)
+ * __attribute__((weak));
+ *
+ * Stack pointer is not yet initialized at this moment
+ * Don't save anything to stack even if compiled with -O0
+ *
+ *************************************************************************/
+ENTRY(soc_init)
+ mov r9, lr
+ bl cpu_init_cp15
+ mov pc, r9 @ back to my caller
+ENDPROC(soc_init)
+ .weak soc_init
+
+/*************************************************************************
+ *
* cpu_init_cp15
*
* Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
--
2.1.0
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