This patch support the SPL features for iMX6SL.
It tested to boot on SD1, SD2 and SD3 mmc ports.
---
board/freescale/mx6slevk/mx6slevk.c | 168 +++++++++++++++++++++++++++++++++++-
1 file changed, 167 insertions(+), 1 deletion(-)
diff --git a/board/freescale/mx6slevk/mx6slevk.c
b/board/freescale/mx6slevk/mx6slevk.c
index e76c343..2c11c4a 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ gd->ram_size = imx_ddr_size();
return 0;
}
@@ -275,3 +275,169 @@ int checkboard(void)
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+
+#define BOOT_CFG 0x20D8004
+#define __REG(x) (*((volatile u32 *)(x)))
+
+struct fsl_esdhc_cfg spl_usdhc_cfg;
+/*
+ * Got it from imximage.cfg file
+ */
+static void spl_dram_mx6slevk(void)
+{
+ __REG(0x020e0344) = 0x00003030;
+ __REG(0x020e0348) = 0x00003030;
+ __REG(0x020e034c) = 0x00003030;
+ __REG(0x020e0350) = 0x00003030;
+ __REG(0x020e030c) = 0x00000030;
+ __REG(0x020e0310) = 0x00000030;
+ __REG(0x020e0314) = 0x00000030;
+ __REG(0x020e0318) = 0x00000030;
+ __REG(0x020e0300) = 0x00000030;
+ __REG(0x020e031c) = 0x00000030;
+ __REG(0x020e0338) = 0x00000028;
+ __REG(0x020e0320) = 0x00000030;
+ __REG(0x020e032c) = 0x00000000;
+ __REG(0x020e033c) = 0x00000008;
+ __REG(0x020e0340) = 0x00000008;
+ __REG(0x020e05c4) = 0x00000030;
+ __REG(0x020e05cc) = 0x00000030;
+ __REG(0x020e05d4) = 0x00000030;
+ __REG(0x020e05d8) = 0x00000030;
+ __REG(0x020e05ac) = 0x00000030;
+ __REG(0x020e05c8) = 0x00000030;
+ __REG(0x020e05b0) = 0x00020000;
+ __REG(0x020e05b4) = 0x00000000;
+ __REG(0x020e05c0) = 0x00020000;
+ __REG(0x020e05d0) = 0x00080000;
+
+ __REG(0x021b001c) = 0x00008000;
+ __REG(0x021b085c) = 0x1b4700c7;
+ __REG(0x021b0800) = 0xa1390003;
+ __REG(0x021b0890) = 0x00300000;
+ __REG(0x021b08b8) = 0x00000800;
+ __REG(0x021b081c) = 0x33333333;
+ __REG(0x021b0820) = 0x33333333;
+ __REG(0x021b0824) = 0x33333333;
+ __REG(0x021b0828) = 0x33333333;
+ __REG(0x021b082c) = 0xf3333333;
+ __REG(0x021b0830) = 0xf3333333;
+ __REG(0x021b0834) = 0xf3333333;
+ __REG(0x021b0838) = 0xf3333333;
+ __REG(0x021b0848) = 0x4241444a;
+ __REG(0x021b0850) = 0x3030312b;
+ __REG(0x021b083c) = 0x20000000;
+ __REG(0x021b0840) = 0x00000000;
+ __REG(0x021b08c0) = 0x24911492;
+ __REG(0x021b08b8) = 0x00000800;
+ __REG(0x021b000c) = 0x33374133;
+ __REG(0x021b0004) = 0x00020024;
+ __REG(0x021b0010) = 0x00100A82;
+ __REG(0x021b0014) = 0x00000093;
+ __REG(0x021b0018) = 0x00001688;
+ __REG(0x021b002c) = 0x0f9f26d2;
+ __REG(0x021b0030) = 0x0000020e;
+ __REG(0x021b0038) = 0x00190778;
+ __REG(0x021b0008) = 0x00000000;
+ __REG(0x021b0040) = 0x0000004f;
+ __REG(0x021b0000) = 0xc3110000;
+ __REG(0x021b001c) = 0x003f8030;
+ __REG(0x021b001c) = 0xff0a8030;
+ __REG(0x021b001c) = 0x82018030;
+ __REG(0x021b001c) = 0x04028030;
+ __REG(0x021b001c) = 0x02038030;
+ __REG(0x021b001c) = 0xff0a8038;
+ __REG(0x021b001c) = 0x82018038;
+ __REG(0x021b001c) = 0x04028038;
+ __REG(0x021b001c) = 0x02038038;
+ __REG(0x021b0800) = 0xa1310003;
+ __REG(0x021b0020) = 0x00001800;
+ __REG(0x021b0818) = 0x00000000;
+ __REG(0x021b08b8) = 0x00000800;
+ __REG(0x021b0004) = 0x00025564;
+ __REG(0x021b0404) = 0x00011006;
+ __REG(0x021b001c) = 0x00000000;
+}
+
+/*
+ * This section require the differentiation
+ * between iMX6 SL.
+ * But for now, it will configure only for
+ * iMX6SL-evk.
+ */
+static void spl_dram_init(void)
+{
+ spl_dram_mx6slevk();
+}
+
+int spl_board_mmc_init(bd_t *bis)
+{
+ unsigned reg = readl(BOOT_CFG) >> 11;
+ /*
+ * Upon reading BOOT_CFG register the following map is done:
+ * Bit 11 and 12 of BOOT_CFG register can determine the current
+ * mmc port
+ * 0x0 SD1
+ * 0x1 SD2
+ * 0x2 SD3
+ */
+
+ switch (reg & 0x3) {
+ case 0x0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ spl_usdhc_cfg.esdhc_base = USDHC1_BASE_ADDR;
+ spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ gd->arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk;
+ break;
+ case 0x1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ spl_usdhc_cfg.esdhc_base = USDHC2_BASE_ADDR;
+ spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk;
+ break;
+ case 0x2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ spl_usdhc_cfg.esdhc_base = USDHC3_BASE_ADDR;
+ spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ gd->arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk;
+ break;
+ }
+
+ return fsl_esdhc_initialize(bis, &spl_usdhc_cfg);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
+#endif
--
1.9.1
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