add a macro define inclusion to compile the function.
iMX6SL doesn't have an MMDC_P1_BASE_ADDR in the header.
It will break the build if the SPL features is enabled
for iMX6SL.
---
arch/arm/cpu/armv7/mx6/ddr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 7a9b03a..3beeded 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -182,6 +182,7 @@ void mx6sdl_dram_iocfg(unsigned width,
* For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
* section titled MMDC initialization
*/
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
@@ -489,3 +490,4 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
/* wait for auto-ZQ calibration to complete */
mdelay(1);
}
+#endif
--
1.9.1
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