Hi! This patchset adds the driver for the Designware master SPI controller. This IP core is integrated on the Altera SoCFPGA. This implementation is a driver model (DM) implementation. So multiple SPI drivers can be used. Thats necessary, since SoCFPGA also integrates the Cadence QSPI controller used to connect the SPI NOR flashes. Without DM, using multiple SPI driver is not possible.
As mentioned above, this patchset depends on the SoCFPGA DT support. And its also done on-top of the Cadence QSPI support I posted a short while ago. But it doesn't depend on it. Its just that the patch series will most likely generate merge conflicts if not applied in this sequence. This is tested on the SoCrates SoCFPGA board using the SPI pins on the P14 header. Thanks, Stefan Cc: Chin Liang See <cl...@altera.com> Cc: Dinh Nguyen <dingu...@altera.com> Cc: Vince Bridgers <vbrid...@altera.com> Cc: Marek Vasut <ma...@denx.de> Cc: Pavel Machek <pa...@denx.de> Cc: Simon Glass <s...@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.t...@gmail.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
