According to the current deep sleep framework, the setting for CCI-400
registers will not execute when waking up. This patch moves the setting
for CCI-400 Slave interfaces to board_early_init_f() which executes
before dram_init(). This patch also moves the setting for enabling
barrier transaction to fsl_dp_resume() which executes after dram_init().
Signed-off-by: Alison Wang <alison.w...@freescale.com>
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++
board/freescale/ls1021aqds/ls1021aqds.c | 28 ++++++++++++++++-------
2 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 2a1082f..a6068a2 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -453,6 +453,8 @@ struct ccsr_ddr {
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define CCI400_CTRLORD_EN_BARRIER 0
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
+#define CCI400_SNOOP_REQ_EN 0x00000001
/* CCI-400 registers */
struct ccsr_cci400 {
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index 8fe59a5..485f412 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -188,6 +188,21 @@ int board_early_init_f(void)
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
+ /*
+ * Enable snoop requests and DVM message requests for
+ * Slave insterface S4 (A7 core cluster)
+ */
+ out_le32(&cci->slave[4].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+ /*
+ * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+ * All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
/* Workaround for the issue that DDR could not respond to
* barrier transaction which is generated by executing DSB/ISB
* instruction. Set CCI-400 control override register to
@@ -511,14 +526,6 @@ int board_init(void)
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
- out_le32(0x1185000, 0x3);
- /*
- * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
- * All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@@ -658,10 +665,15 @@ int fsl_dp_resume(void)
u32 start_addr;
void (*kernel_resume)(void);
struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
if (!is_warm_boot())
return 0;
+ /* Set CCI-400 control override register to
+ * enable barrier transaction */
+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
#ifdef CONFIG_LS102XA_NS_ACESS
enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
#endif
--
2.1.0.27.g96db324
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