This patch includes the latest DT sources for socfpga from the current
Linux kernel. And enables CONFIG_OF_CONTROL for socfpga_cyclone5 to
make use of this new DT support.

Note that now the image to use is u-boot-dtb.img!

Signed-off-by: Stefan Roese <s...@denx.de>
Cc: Marek Vasut <ma...@denx.de>
Cc: Chin Liang See <cl...@altera.com>
Cc: Dinh Nguyen <dingu...@altera.com>
Cc: Vince Bridgers <vbrid...@altera.com>
Cc: Albert Aribaud <albert.u.b...@aribaud.net>
Cc: Pavel Machek <pa...@denx.de>
---
 arch/arm/dts/Makefile                    |   2 +
 arch/arm/dts/socfpga.dtsi                | 755 +++++++++++++++++++++++++++++++
 arch/arm/dts/socfpga_cyclone5.dtsi       |  51 +++
 arch/arm/dts/socfpga_cyclone5_socdk.dts  |  90 ++++
 configs/socfpga_cyclone5_defconfig       |   2 +
 include/dt-bindings/reset/altr,rst-mgr.h |  90 ++++
 6 files changed, 990 insertions(+)
 create mode 100644 arch/arm/dts/socfpga.dtsi
 create mode 100644 arch/arm/dts/socfpga_cyclone5.dtsi
 create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk.dts
 create mode 100644 include/dt-bindings/reset/altr,rst-mgr.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c346063..a208ff7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -39,6 +39,8 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
        zynq-zc770-xm013.dtb
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
+dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socdk.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
new file mode 100644
index 0000000..4472fd9
--- /dev/null
+++ b/arch/arm/dts/socfpga.dtsi
@@ -0,0 +1,755 @@
+/*
+ *  Copyright (C) 2012 Altera <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/reset/altr,rst-mgr.h>
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       aliases {
+               ethernet0 = &gmac0;
+               ethernet1 = &gmac1;
+               serial0 = &uart0;
+               serial1 = &uart1;
+               timer0 = &timer0;
+               timer1 = &timer1;
+               timer2 = &timer2;
+               timer3 = &timer3;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       compatible = "arm,cortex-a9";
+                       device_type = "cpu";
+                       reg = <0>;
+                       next-level-cache = <&L2>;
+               };
+               cpu@1 {
+                       compatible = "arm,cortex-a9";
+                       device_type = "cpu";
+                       reg = <1>;
+                       next-level-cache = <&L2>;
+               };
+       };
+
+       intc: intc@fffed000 {
+               compatible = "arm,cortex-a9-gic";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0xfffed000 0x1000>,
+                     <0xfffec100 0x100>;
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               device_type = "soc";
+               interrupt-parent = <&intc>;
+               ranges;
+
+               amba {
+                       compatible = "arm,amba-bus";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       pdma: pdma@ffe01000 {
+                               compatible = "arm,pl330", "arm,primecell";
+                               reg = <0xffe01000 0x1000>;
+                               interrupts = <0 104 4>,
+                                            <0 105 4>,
+                                            <0 106 4>,
+                                            <0 107 4>,
+                                            <0 108 4>,
+                                            <0 109 4>,
+                                            <0 110 4>,
+                                            <0 111 4>;
+                               #dma-cells = <1>;
+                               #dma-channels = <8>;
+                               #dma-requests = <32>;
+                               clocks = <&l4_main_clk>;
+                               clock-names = "apb_pclk";
+                       };
+               };
+
+               can0: can@ffc00000 {
+                       compatible = "bosch,d_can";
+                       reg = <0xffc00000 0x1000>;
+                       interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
+                       clocks = <&can0_clk>;
+                       status = "disabled";
+               };
+
+               can1: can@ffc01000 {
+                       compatible = "bosch,d_can";
+                       reg = <0xffc01000 0x1000>;
+                       interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
+                       clocks = <&can1_clk>;
+                       status = "disabled";
+               };
+
+               clkmgr@ffd04000 {
+                               compatible = "altr,clk-mgr";
+                               reg = <0xffd04000 0x1000>;
+
+                               clocks {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       osc1: osc1 {
+                                               #clock-cells = <0>;
+                                               compatible = "fixed-clock";
+                                       };
+
+                                       osc2: osc2 {
+                                               #clock-cells = <0>;
+                                               compatible = "fixed-clock";
+                                       };
+
+                                       f2s_periph_ref_clk: f2s_periph_ref_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "fixed-clock";
+                                       };
+
+                                       f2s_sdram_ref_clk: f2s_sdram_ref_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "fixed-clock";
+                                       };
+
+                                       main_pll: main_pll {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-pll-clock";
+                                               clocks = <&osc1>;
+                                               reg = <0x40>;
+
+                                               mpuclk: mpuclk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&main_pll>;
+                                                       div-reg = <0xe0 0 9>;
+                                                       reg = <0x48>;
+                                               };
+
+                                               mainclk: mainclk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&main_pll>;
+                                                       div-reg = <0xe4 0 9>;
+                                                       reg = <0x4C>;
+                                               };
+
+                                               dbg_base_clk: dbg_base_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&main_pll>;
+                                                       div-reg = <0xe8 0 9>;
+                                                       reg = <0x50>;
+                                               };
+
+                                               main_qspi_clk: main_qspi_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&main_pll>;
+                                                       reg = <0x54>;
+                                               };
+
+                                               main_nand_sdmmc_clk: 
main_nand_sdmmc_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&main_pll>;
+                                                       reg = <0x58>;
+                                               };
+
+                                               cfg_h2f_usr0_clk: 
cfg_h2f_usr0_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&main_pll>;
+                                                       reg = <0x5C>;
+                                               };
+                                       };
+
+                                       periph_pll: periph_pll {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-pll-clock";
+                                               clocks = <&osc1>, <&osc2>, 
<&f2s_periph_ref_clk>;
+                                               reg = <0x80>;
+
+                                               emac0_clk: emac0_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&periph_pll>;
+                                                       reg = <0x88>;
+                                               };
+
+                                               emac1_clk: emac1_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&periph_pll>;
+                                                       reg = <0x8C>;
+                                               };
+
+                                               per_qspi_clk: per_qsi_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&periph_pll>;
+                                                       reg = <0x90>;
+                                               };
+
+                                               per_nand_mmc_clk: 
per_nand_mmc_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&periph_pll>;
+                                                       reg = <0x94>;
+                                               };
+
+                                               per_base_clk: per_base_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&periph_pll>;
+                                                       reg = <0x98>;
+                                               };
+
+                                               h2f_usr1_clk: h2f_usr1_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&periph_pll>;
+                                                       reg = <0x9C>;
+                                               };
+                                       };
+
+                                       sdram_pll: sdram_pll {
+                                               #address-cells = <1>;
+                                               #size-cells = <0>;
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-pll-clock";
+                                               clocks = <&osc1>, <&osc2>, 
<&f2s_sdram_ref_clk>;
+                                               reg = <0xC0>;
+
+                                               ddr_dqs_clk: ddr_dqs_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&sdram_pll>;
+                                                       reg = <0xC8>;
+                                               };
+
+                                               ddr_2x_dqs_clk: ddr_2x_dqs_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&sdram_pll>;
+                                                       reg = <0xCC>;
+                                               };
+
+                                               ddr_dq_clk: ddr_dq_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&sdram_pll>;
+                                                       reg = <0xD0>;
+                                               };
+
+                                               h2f_usr2_clk: h2f_usr2_clk {
+                                                       #clock-cells = <0>;
+                                                       compatible = 
"altr,socfpga-perip-clk";
+                                                       clocks = <&sdram_pll>;
+                                                       reg = <0xD4>;
+                                               };
+                                       };
+
+                                       mpu_periph_clk: mpu_periph_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-perip-clk";
+                                               clocks = <&mpuclk>;
+                                               fixed-divider = <4>;
+                                       };
+
+                                       mpu_l2_ram_clk: mpu_l2_ram_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-perip-clk";
+                                               clocks = <&mpuclk>;
+                                               fixed-divider = <2>;
+                                       };
+
+                                       l4_main_clk: l4_main_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&mainclk>;
+                                               clk-gate = <0x60 0>;
+                                       };
+
+                                       l3_main_clk: l3_main_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-perip-clk";
+                                               clocks = <&mainclk>;
+                                               fixed-divider = <1>;
+                                       };
+
+                                       l3_mp_clk: l3_mp_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&mainclk>;
+                                               div-reg = <0x64 0 2>;
+                                               clk-gate = <0x60 1>;
+                                       };
+
+                                       l3_sp_clk: l3_sp_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&mainclk>;
+                                               div-reg = <0x64 2 2>;
+                                       };
+
+                                       l4_mp_clk: l4_mp_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&mainclk>, 
<&per_base_clk>;
+                                               div-reg = <0x64 4 3>;
+                                               clk-gate = <0x60 2>;
+                                       };
+
+                                       l4_sp_clk: l4_sp_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&mainclk>, 
<&per_base_clk>;
+                                               div-reg = <0x64 7 3>;
+                                               clk-gate = <0x60 3>;
+                                       };
+
+                                       dbg_at_clk: dbg_at_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&dbg_base_clk>;
+                                               div-reg = <0x68 0 2>;
+                                               clk-gate = <0x60 4>;
+                                       };
+
+                                       dbg_clk: dbg_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&dbg_base_clk>;
+                                               div-reg = <0x68 2 2>;
+                                               clk-gate = <0x60 5>;
+                                       };
+
+                                       dbg_trace_clk: dbg_trace_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&dbg_base_clk>;
+                                               div-reg = <0x6C 0 3>;
+                                               clk-gate = <0x60 6>;
+                                       };
+
+                                       dbg_timer_clk: dbg_timer_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&dbg_base_clk>;
+                                               clk-gate = <0x60 7>;
+                                       };
+
+                                       cfg_clk: cfg_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&cfg_h2f_usr0_clk>;
+                                               clk-gate = <0x60 8>;
+                                       };
+
+                                       h2f_user0_clk: h2f_user0_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&cfg_h2f_usr0_clk>;
+                                               clk-gate = <0x60 9>;
+                                       };
+
+                                       emac_0_clk: emac_0_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&emac0_clk>;
+                                               clk-gate = <0xa0 0>;
+                                       };
+
+                                       emac_1_clk: emac_1_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&emac1_clk>;
+                                               clk-gate = <0xa0 1>;
+                                       };
+
+                                       usb_mp_clk: usb_mp_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&per_base_clk>;
+                                               clk-gate = <0xa0 2>;
+                                               div-reg = <0xa4 0 3>;
+                                       };
+
+                                       spi_m_clk: spi_m_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&per_base_clk>;
+                                               clk-gate = <0xa0 3>;
+                                               div-reg = <0xa4 3 3>;
+                                       };
+
+                                       can0_clk: can0_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&per_base_clk>;
+                                               clk-gate = <0xa0 4>;
+                                               div-reg = <0xa4 6 3>;
+                                       };
+
+                                       can1_clk: can1_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&per_base_clk>;
+                                               clk-gate = <0xa0 5>;
+                                               div-reg = <0xa4 9 3>;
+                                       };
+
+                                       gpio_db_clk: gpio_db_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&per_base_clk>;
+                                               clk-gate = <0xa0 6>;
+                                               div-reg = <0xa8 0 24>;
+                                       };
+
+                                       h2f_user1_clk: h2f_user1_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&h2f_usr1_clk>;
+                                               clk-gate = <0xa0 7>;
+                                       };
+
+                                       sdmmc_clk: sdmmc_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&f2s_periph_ref_clk>, 
<&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                               clk-gate = <0xa0 8>;
+                                               clk-phase = <0 135>;
+                                       };
+
+                                       nand_x_clk: nand_x_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&f2s_periph_ref_clk>, 
<&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                               clk-gate = <0xa0 9>;
+                                       };
+
+                                       nand_clk: nand_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&f2s_periph_ref_clk>, 
<&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                               clk-gate = <0xa0 10>;
+                                               fixed-divider = <4>;
+                                       };
+
+                                       qspi_clk: qspi_clk {
+                                               #clock-cells = <0>;
+                                               compatible = 
"altr,socfpga-gate-clk";
+                                               clocks = <&f2s_periph_ref_clk>, 
<&main_qspi_clk>, <&per_qspi_clk>;
+                                               clk-gate = <0xa0 11>;
+                                       };
+                               };
+                       };
+
+               gmac0: ethernet@ff700000 {
+                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", 
"snps,dwmac";
+                       altr,sysmgr-syscon = <&sysmgr 0x60 0>;
+                       reg = <0xff700000 0x2000>;
+                       interrupts = <0 115 4>;
+                       interrupt-names = "macirq";
+                       mac-address = [00 00 00 00 00 00];/* Filled in by 
U-Boot */
+                       clocks = <&emac0_clk>;
+                       clock-names = "stmmaceth";
+                       resets = <&rst EMAC0_RESET>;
+                       reset-names = "stmmaceth";
+                       snps,multicast-filter-bins = <256>;
+                       snps,perfect-filter-entries = <128>;
+                       status = "disabled";
+               };
+
+               gmac1: ethernet@ff702000 {
+                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", 
"snps,dwmac";
+                       altr,sysmgr-syscon = <&sysmgr 0x60 2>;
+                       reg = <0xff702000 0x2000>;
+                       interrupts = <0 120 4>;
+                       interrupt-names = "macirq";
+                       mac-address = [00 00 00 00 00 00];/* Filled in by 
U-Boot */
+                       clocks = <&emac1_clk>;
+                       clock-names = "stmmaceth";
+                       resets = <&rst EMAC1_RESET>;
+                       reset-names = "stmmaceth";
+                       snps,multicast-filter-bins = <256>;
+                       snps,perfect-filter-entries = <128>;
+                       status = "disabled";
+               };
+
+               i2c0: i2c@ffc04000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc04000 0x1000>;
+                       clocks = <&l4_sp_clk>;
+                       interrupts = <0 158 0x4>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@ffc05000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc05000 0x1000>;
+                       clocks = <&l4_sp_clk>;
+                       interrupts = <0 159 0x4>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@ffc06000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc06000 0x1000>;
+                       clocks = <&l4_sp_clk>;
+                       interrupts = <0 160 0x4>;
+                       status = "disabled";
+               };
+
+               i2c3: i2c@ffc07000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,designware-i2c";
+                       reg = <0xffc07000 0x1000>;
+                       clocks = <&l4_sp_clk>;
+                       interrupts = <0 161 0x4>;
+                       status = "disabled";
+               };
+
+               gpio0: gpio@ff708000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0xff708000 0x1000>;
+                       clocks = <&per_base_clk>;
+                       status = "disabled";
+
+                       porta: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <29>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <0 164 4>;
+                       };
+               };
+
+               gpio1: gpio@ff709000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0xff709000 0x1000>;
+                       clocks = <&per_base_clk>;
+                       status = "disabled";
+
+                       portb: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <29>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <0 165 4>;
+                       };
+               };
+
+               gpio2: gpio@ff70a000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "snps,dw-apb-gpio";
+                       reg = <0xff70a000 0x1000>;
+                       clocks = <&per_base_clk>;
+                       status = "disabled";
+
+                       portc: gpio-controller@0 {
+                               compatible = "snps,dw-apb-gpio-port";
+                               gpio-controller;
+                               #gpio-cells = <2>;
+                               snps,nr-gpios = <27>;
+                               reg = <0>;
+                               interrupt-controller;
+                               #interrupt-cells = <2>;
+                               interrupts = <0 166 4>;
+                       };
+               };
+
+               sdr: sdr@ffc25000 {
+                       compatible = "syscon";
+                       reg = <0xffc25000 0x1000>;
+               };
+
+               sdramedac {
+                       compatible = "altr,sdram-edac";
+                       altr,sdr-syscon = <&sdr>;
+                       interrupts = <0 39 4>;
+               };
+
+               L2: l2-cache@fffef000 {
+                       compatible = "arm,pl310-cache";
+                       reg = <0xfffef000 0x1000>;
+                       interrupts = <0 38 0x04>;
+                       cache-unified;
+                       cache-level = <2>;
+                       arm,tag-latency = <1 1 1>;
+                       arm,data-latency = <2 1 1>;
+               };
+
+               mmc: dwmmc0@ff704000 {
+                       compatible = "altr,socfpga-dw-mshc";
+                       reg = <0xff704000 0x1000>;
+                       interrupts = <0 139 4>;
+                       fifo-depth = <0x400>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+                       clock-names = "biu", "ciu";
+               };
+
+               /* Local timer */
+               timer@fffec600 {
+                       compatible = "arm,cortex-a9-twd-timer";
+                       reg = <0xfffec600 0x100>;
+                       interrupts = <1 13 0xf04>;
+                       clocks = <&mpu_periph_clk>;
+               };
+
+               timer0: timer0@ffc08000 {
+                       compatible = "snps,dw-apb-timer";
+                       interrupts = <0 167 4>;
+                       reg = <0xffc08000 0x1000>;
+                       clocks = <&l4_sp_clk>;
+                       clock-names = "timer";
+               };
+
+               timer1: timer1@ffc09000 {
+                       compatible = "snps,dw-apb-timer";
+                       interrupts = <0 168 4>;
+                       reg = <0xffc09000 0x1000>;
+                       clocks = <&l4_sp_clk>;
+                       clock-names = "timer";
+               };
+
+               timer2: timer2@ffd00000 {
+                       compatible = "snps,dw-apb-timer";
+                       interrupts = <0 169 4>;
+                       reg = <0xffd00000 0x1000>;
+                       clocks = <&osc1>;
+                       clock-names = "timer";
+               };
+
+               timer3: timer3@ffd01000 {
+                       compatible = "snps,dw-apb-timer";
+                       interrupts = <0 170 4>;
+                       reg = <0xffd01000 0x1000>;
+                       clocks = <&osc1>;
+                       clock-names = "timer";
+               };
+
+               uart0: serial0@ffc02000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0xffc02000 0x1000>;
+                       interrupts = <0 162 4>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&l4_sp_clk>;
+               };
+
+               uart1: serial1@ffc03000 {
+                       compatible = "snps,dw-apb-uart";
+                       reg = <0xffc03000 0x1000>;
+                       interrupts = <0 163 4>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&l4_sp_clk>;
+               };
+
+               rst: rstmgr@ffd05000 {
+                       #reset-cells = <1>;
+                       compatible = "altr,rst-mgr";
+                       reg = <0xffd05000 0x1000>;
+               };
+
+               usbphy0: usbphy@0 {
+                       #phy-cells = <0>;
+                       compatible = "usb-nop-xceiv";
+                       status = "okay";
+               };
+
+               usb0: usb@ffb00000 {
+                       compatible = "snps,dwc2";
+                       reg = <0xffb00000 0xffff>;
+                       interrupts = <0 125 4>;
+                       clocks = <&usb_mp_clk>;
+                       clock-names = "otg";
+                       phys = <&usbphy0>;
+                       phy-names = "usb2-phy";
+                       status = "disabled";
+               };
+
+               usb1: usb@ffb40000 {
+                       compatible = "snps,dwc2";
+                       reg = <0xffb40000 0xffff>;
+                       interrupts = <0 128 4>;
+                       clocks = <&usb_mp_clk>;
+                       clock-names = "otg";
+                       phys = <&usbphy0>;
+                       phy-names = "usb2-phy";
+                       status = "disabled";
+               };
+
+               watchdog0: watchdog@ffd02000 {
+                       compatible = "snps,dw-wdt";
+                       reg = <0xffd02000 0x1000>;
+                       interrupts = <0 171 4>;
+                       clocks = <&osc1>;
+                       status = "disabled";
+               };
+
+               watchdog1: watchdog@ffd03000 {
+                       compatible = "snps,dw-wdt";
+                       reg = <0xffd03000 0x1000>;
+                       interrupts = <0 172 4>;
+                       clocks = <&osc1>;
+                       status = "disabled";
+               };
+
+               sysmgr: sysmgr@ffd08000 {
+                       compatible = "altr,sys-mgr", "syscon";
+                       reg = <0xffd08000 0x4000>;
+               };
+       };
+};
diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi 
b/arch/arm/dts/socfpga_cyclone5.dtsi
new file mode 100644
index 0000000..28c05e7
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5.dtsi
@@ -0,0 +1,51 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+#include "socfpga.dtsi"
+
+/ {
+       soc {
+               clkmgr@ffd04000 {
+                       clocks {
+                               osc1 {
+                                       clock-frequency = <25000000>;
+                               };
+                       };
+               };
+
+               mmc0: dwmmc0@ff704000 {
+                       num-slots = <1>;
+                       broken-cd;
+                       bus-width = <4>;
+                       cap-mmc-highspeed;
+                       cap-sd-highspeed;
+               };
+
+               ethernet@ff702000 {
+                       phy-mode = "rgmii";
+                       phy-addr = <0xffffffff>; /* probe for phy addr */
+                       status = "okay";
+               };
+
+               sysmgr@ffd08000 {
+                       cpu1-start-addr = <0xffd080c4>;
+               };
+       };
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts 
b/arch/arm/dts/socfpga_cyclone5_socdk.dts
new file mode 100644
index 0000000..258865d
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -0,0 +1,90 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+       model = "Altera SOCFPGA Cyclone V SoC Development Kit";
+       compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+       chosen {
+               bootargs = "console=ttyS0,115200";
+       };
+
+       memory {
+               name = "memory";
+               device_type = "memory";
+               reg = <0x0 0x40000000>; /* 1GB */
+       };
+
+       aliases {
+               /* this allow the ethaddr uboot environmnet variable contents
+                * to be added to the gmac1 device tree blob.
+                */
+               ethernet0 = &gmac1;
+       };
+
+       regulator_3_3v: 3-3-v-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+};
+
+&gmac1 {
+       status = "okay";
+       phy-mode = "rgmii";
+
+       rxd0-skew-ps = <0>;
+       rxd1-skew-ps = <0>;
+       rxd2-skew-ps = <0>;
+       rxd3-skew-ps = <0>;
+       txen-skew-ps = <0>;
+       txc-skew-ps = <2600>;
+       rxdv-skew-ps = <0>;
+       rxc-skew-ps = <2000>;
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&i2c0 {
+       status = "okay";
+
+       eeprom@51 {
+               compatible = "atmel,24c32";
+               reg = <0x51>;
+               pagesize = <32>;
+       };
+
+       rtc@68 {
+               compatible = "dallas,ds1339";
+               reg = <0x68>;
+       };
+};
+
+&mmc0 {
+       cd-gpios = <&portb 18 0>;
+       vmmc-supply = <&regulator_3_3v>;
+       vqmmc-supply = <&regulator_3_3v>;
+};
+
+&usb1 {
+       status = "okay";
+};
diff --git a/configs/socfpga_cyclone5_defconfig 
b/configs/socfpga_cyclone5_defconfig
index 4b2ede4..2d3dd47 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
diff --git a/include/dt-bindings/reset/altr,rst-mgr.h 
b/include/dt-bindings/reset/altr,rst-mgr.h
new file mode 100644
index 0000000..3f04908
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar <s.trumt...@pengutronix.de>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
+
+/* MPUMODRST */
+#define CPU0_RESET             0
+#define CPU1_RESET             1
+#define WDS_RESET              2
+#define SCUPER_RESET           3
+#define L2_RESET               4
+
+/* PERMODRST */
+#define EMAC0_RESET            32
+#define EMAC1_RESET            33
+#define USB0_RESET             34
+#define USB1_RESET             35
+#define NAND_RESET             36
+#define QSPI_RESET             37
+#define L4WD0_RESET            38
+#define L4WD1_RESET            39
+#define OSC1TIMER0_RESET       40
+#define OSC1TIMER1_RESET       41
+#define SPTIMER0_RESET         42
+#define SPTIMER1_RESET         43
+#define I2C0_RESET             44
+#define I2C1_RESET             45
+#define I2C2_RESET             46
+#define I2C3_RESET             47
+#define UART0_RESET            48
+#define UART1_RESET            49
+#define SPIM0_RESET            50
+#define SPIM1_RESET            51
+#define SPIS0_RESET            52
+#define SPIS1_RESET            53
+#define SDMMC_RESET            54
+#define CAN0_RESET             55
+#define CAN1_RESET             56
+#define GPIO0_RESET            57
+#define GPIO1_RESET            58
+#define GPIO2_RESET            59
+#define DMA_RESET              60
+#define SDR_RESET              61
+
+/* PER2MODRST */
+#define DMAIF0_RESET           64
+#define DMAIF1_RESET           65
+#define DMAIF2_RESET           66
+#define DMAIF3_RESET           67
+#define DMAIF4_RESET           68
+#define DMAIF5_RESET           69
+#define DMAIF6_RESET           70
+#define DMAIF7_RESET           71
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET         96
+#define LWHPS2FPGA_RESET       97
+#define FPGA2HPS_RESET         98
+
+/* MISCMODRST*/
+#define ROM_RESET              128
+#define OCRAM_RESET            129
+#define SYSMGR_RESET           130
+#define SYSMGRCOLD_RESET       131
+#define FPGAMGR_RESET          132
+#define ACPIDMAP_RESET         133
+#define S2F_RESET              134
+#define S2FCOLD_RESET          135
+#define NRSTPIN_RESET          136
+#define TIMESTAMPCOLD_RESET    137
+#define CLKMGRCOLD_RESET       138
+#define SCANMGR_RESET          139
+#define FRZCTRLCOLD_RESET      140
+#define SYSDBG_RESET           141
+#define DBG_RESET              142
+#define TAPCOLD_RESET          143
+#define SDRCOLD_RESET          144
+
+#endif
-- 
2.1.3

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