Le Tue, 26 Aug 2014 17:33:48 +0200, Thierry Reding <thierry.red...@gmail.com> a écrit :
> From: Thierry Reding <tred...@nvidia.com> > > This series adds PCIe support for Tegra20, Tegra30 and Tegra124. The > size is mostly due to the large number of infrastructure that's added > (libfdt, Tegra specific drivers required by the PCIe driver). In this > version I've included all patches that were previously split into > three separate series. Spreading them over multiple series is > probably not worth it since there might be some dependencies between > them and only the end result gives a completely working setup. > > Patch 1 adds a %pa modifier to printf() to print physical addresses. > This is required to allow code to output such addresses irrespective > of whether a 64 bit or 32 bit architecture is built for. > > Patches 2-7 add various FDT helpers to make it easier to parse > complex device trees. > > Patch 8 is a minor cleanup to the PCI command that prevents a spew of > error messages if a bus does not exist. Patch 9 modifies the PCI > enumeration code to honor theh restrictions encoded within a host > controller driver's pci_ski_dev() implementation. This is required to > prevent exceptions from the NVIDIA Tegra PCIe controller. > > Patch 10 imports the pr_fmt() macro used within the Linux kernel to > reduce the number of characters consumed by literal strings by > allowing a source file to specify a prefix or suffix that should be > applied to all format strings in the file. It is currently used by > the debug() and error() macros. > > Patches 11-14 are some cleanup and refactoring of I2C core code, the > addition of a higher level API that makes it easier for I2C client > drivers to talk to devices. The Tegra I2C driver now implements > i2c_get_bus_num_fdt() to obtain bus numbers corresponding to a DT > node. > > Patch 15 implements a driver for the AS3722 PMIC used on the Venice2 > and Jetson TK1 boards. > > Patches 16-21 are preparatory work for the Tegra PCIe controller. > They add missing clock driver functionality as well as drivers for > the Tegra powergate and XUSB pad controller blocks. > > Patch 22 adds the PCIe controller driver for Tegra20, Tegra30 and > Tegra124. > > Device tree nodes and configurations options to enable PCIe on the > TrimSlice (Tegra20), Beaver, Cardhu (Tegra30) and Jetson TK1 > (Tegra124) boards are added in patches 23-31. > > Patches 32-35 implement non-cached memory support that will be used > in the last batch of patches to implement more reliable packet > transfers in the r8169 driver. Patch 36 enables non-cached memory > support on Tegra. > > Finally, patches 37-40 implement non-cached memory support and > various fixes in the r8169 driver and add support for the revision of > the NIC found on the Jetson TK1. > > The above boards all have an ethernet NIC connected to PCIe, which is > what I tested with. > > Thierry Reding (40): > vsprintf: Add modifier for phys_addr_t > fdt: Add a function to count strings > fdt: Add a function to get the index of a string > fdt: Add functions to retrieve strings > fdt: Add resource parsing functions > fdt: Add a function to return PCI BDF triplet > fdt: Add a subnodes iterator macro > pci: Abort early if bus does not exist > pci: Honour pci_skip_dev() > Add pr_fmt() macro > i2c: Initialize the correct bus > i2c: Refactor adapter initialization > i2c: Add high-level API > i2c: tegra: Implement i2c_get_bus_num_fdt() > power: Add AMS AS3722 PMIC support > ARM: tegra: Implement tegra_plle_enable() > ARM: tegra: Provide PCIEXCLK reset ID > ARM: tegra: Implement powergate support > ARM: tegra: Implement XUSB pad controller > ARM: tegra: Add XUSB pad controller on Tegra124 > ARM: tegra: Enable XUSB pad controller on Jetson TK1 > pci: tegra: Add Tegra PCIe driver > ARM: tegra: Add Tegra20 PCIe device tree node > ARM: tegra: Enable PCIe on TrimSlice > ARM: tegra: Add GIC for Tegra30 > ARM: tegra: Add Tegra30 PCIe device tree node > ARM: tegra: Enable PCIe on Cardhu > ARM: tegra: Enable PCIe on Beaver > ARM: tegra: Add GIC for Tegra124 > ARM: tegra: Add Tegra124 PCIe device tree node > ARM: tegra: Enable PCIe on Jetson TK1 > ARM: cache_v7: Various minor cleanups > ARM: cache-cp15: Use more accurate types > malloc: Output region when debugging > ARM: Implement non-cached memory support > ARM: tegra: Enable non-cached memory > net: rtl8169: Honor CONFIG_SYS_RX_ETH_BUFFER > net: rtl8169: Properly align buffers > net: rtl8169: Use non-cached memory if available > net: rtl8169: Add support for RTL-8168/8111g > > README | 19 + > arch/arm/cpu/armv7/cache_v7.c | 14 +- > arch/arm/cpu/tegra-common/Makefile | 2 + > arch/arm/cpu/tegra-common/powergate.c | 102 ++ > arch/arm/cpu/tegra-common/xusb-padctl.c | 39 + > arch/arm/cpu/tegra124-common/Makefile | 1 + > arch/arm/cpu/tegra124-common/clock.c | 109 +++ > arch/arm/cpu/tegra124-common/xusb-padctl.c | 716 > ++++++++++++++ arch/arm/cpu/tegra20-common/clock.c | > 141 ++- arch/arm/cpu/tegra30-common/clock.c | 155 +++ > arch/arm/dts/tegra124-jetson-tk1.dts | 373 +++++++ > arch/arm/dts/tegra124.dtsi | 90 ++ > arch/arm/dts/tegra20-trimslice.dts | 69 ++ > arch/arm/dts/tegra20.dtsi | 60 ++ > arch/arm/dts/tegra30-beaver.dts | 245 +++++ > arch/arm/dts/tegra30-cardhu.dts | 362 +++++++ > arch/arm/dts/tegra30.dtsi | 84 ++ > arch/arm/include/asm/arch-tegra/powergate.h | 38 + > arch/arm/include/asm/arch-tegra/xusb-padctl.h | 24 + > arch/arm/include/asm/arch-tegra114/powergate.h | 6 + > arch/arm/include/asm/arch-tegra124/clock.h | 2 + > arch/arm/include/asm/arch-tegra124/powergate.h | 6 + > arch/arm/include/asm/arch-tegra20/clock-tables.h | 2 +- > arch/arm/include/asm/arch-tegra20/clock.h | 2 + > arch/arm/include/asm/arch-tegra20/powergate.h | 6 + > arch/arm/include/asm/arch-tegra30/clock.h | 2 + > arch/arm/include/asm/arch-tegra30/powergate.h | 6 + > arch/arm/include/asm/system.h | 7 +- > arch/arm/lib/cache-cp15.c | 6 +- > arch/arm/lib/cache.c | 42 + > board/compulab/trimslice/trimslice.c | 8 + > board/nvidia/cardhu/cardhu.c | 56 ++ > board/nvidia/common/board.c | 3 + > board/nvidia/jetson-tk1/jetson-tk1.c | 52 + > common/board_r.c | 11 + > common/cmd_pci.c | 7 + > common/dlmalloc.c | 3 + > drivers/i2c/i2c_core.c | 80 +- > drivers/i2c/tegra_i2c.c | 13 + > drivers/net/rtl8169.c | 127 ++- > drivers/pci/Makefile | 1 + > drivers/pci/pci.c | 3 + > drivers/pci/pci_tegra.c | 1143 > ++++++++++++++++++++++ > drivers/power/Makefile | 1 + > drivers/power/as3722.c | 300 ++++++ > include/common.h | 14 +- > include/configs/beaver.h | 10 + > include/configs/cardhu.h | 10 + > include/configs/jetson-tk1.h | 13 + > include/configs/tegra-common.h | 1 + > include/configs/trimslice.h | 10 + > include/dt-bindings/clock/tegra124-car.h | 341 +++++++ > include/dt-bindings/clock/tegra20-car.h | 158 +++ > include/dt-bindings/clock/tegra30-car.h | 265 +++++ > include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 7 + > include/fdtdec.h | 69 ++ > include/i2c.h | 96 ++ > include/libfdt.h | 72 ++ > include/pci.h | 1 + > include/power/as3722.h | 27 + > lib/fdtdec.c | 76 ++ > lib/libfdt/fdt_ro.c | 76 ++ > lib/vsprintf.c | 16 +- 63 files > changed, 5736 insertions(+), 64 deletions(-) create mode 100644 > arch/arm/cpu/tegra-common/powergate.c create mode 100644 > arch/arm/cpu/tegra-common/xusb-padctl.c create mode 100644 > arch/arm/cpu/tegra124-common/xusb-padctl.c create mode 100644 > arch/arm/include/asm/arch-tegra/powergate.h create mode 100644 > arch/arm/include/asm/arch-tegra/xusb-padctl.h create mode 100644 > arch/arm/include/asm/arch-tegra114/powergate.h create mode 100644 > arch/arm/include/asm/arch-tegra124/powergate.h create mode 100644 > arch/arm/include/asm/arch-tegra20/powergate.h create mode 100644 > arch/arm/include/asm/arch-tegra30/powergate.h create mode 100644 > drivers/pci/pci_tegra.c create mode 100644 drivers/power/as3722.c > create mode 100644 include/dt-bindings/clock/tegra124-car.h > create mode 100644 include/dt-bindings/clock/tegra20-car.h > create mode 100644 include/dt-bindings/clock/tegra30-car.h > create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h > create mode 100644 include/power/as3722.h Am I right in thinking there will be a V3 series, at least of the part not already awaiting upstream ? If so, maybe it should all be delegated to a single custodian -- right now it is split over five custodians (although part of it -- so that all of it is applied in one go without "foreign" patches getting in between. Amicalement, -- Albert. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
