Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function
to set the start address for secondary cores in the LS1021A specific
manner.
Signed-off-by: Xiubo Li <li.xi...@freescale.com>
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 15 +++++++++++++++
arch/arm/include/asm/arch-ls102xa/config.h | 2 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++
include/configs/ls1021aqds.h | 7 +++++++
include/configs/ls1021atwr.h | 7 +++++++
5 files changed, 34 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index b7dde45..69d1801 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -101,3 +101,18 @@ int cpu_eth_init(bd_t *bis)
return 0;
}
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+/* Setting the address at which secondary cores start from.*/
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+ /*
+ * After setting the secondary cores start address,
+ * just release them to boot.
+ */
+ out_be32(&gur->scratchrw[0], addr);
+ out_be32(&gur->brrl, 0x2);
+}
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index ed78c33..4856388 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -11,6 +11,8 @@
#define OCRAM_BASE_ADDR 0x10000000
#define OCRAM_SIZE 0x00020000
+#define OCRAM_BASE_S_ADDR 0x10010000
+#define OCRAM_S_SIZE 0x00010000
#define CONFIG_SYS_IMMR 0x01000000
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..0bac353 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -17,6 +17,9 @@
#define SOC_VER_LS1021 0x11
#define SOC_VER_LS1022 0x12
+#define CCSR_BRR_OFFSET 0xe4
+#define CCSR_SCRATCHRW1_OFFSET 0x200
+
#define RCWSR0_SYS_PLL_RAT_SHIFT 25
#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
#define RCWSR0_MEM_PLL_RAT_SHIFT 16
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 657e3b6..6976cfa 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -324,6 +324,13 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_CMDLINE_EDITING
#define CONFIG_CMD_IMLS
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_SMP_PEN_ADDR 0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ 12500000
+#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
+
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 45b2272..655b39a 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -227,6 +227,13 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_CMD_IMLS
+#define CONFIG_ARMV7_NONSEC
+#define CONFIG_ARMV7_VIRT
+#define CONFIG_PEN_ADDR_BIG_ENDIAN
+#define CONFIG_SMP_PEN_ADDR 0x01ee0200
+#define CONFIG_TIMER_CLK_FREQ 12500000
+#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
+
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
--
2.1.0.27.g96db324
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