Enable the PL310 L2 cache controller support for the SoCFPGA. With the cache related issues resolved, this is safe to be done.
Signed-off-by: Marek Vasut <ma...@denx.de> Cc: Chin Liang See <cl...@altera.com> Cc: Dinh Nguyen <dingu...@altera.com> Cc: Albert Aribaud <albert.u.b...@aribaud.net> Cc: Tom Rini <tr...@ti.com> Cc: Wolfgang Denk <w...@denx.de> Cc: Pavel Machek <pa...@denx.de> Acked-by: Pavel Machek <pa...@denx.de> --- include/configs/socfpga_cyclone5.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index de60bb2..c8986d9 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -27,6 +27,8 @@ #define CONFIG_SYS_ARM_CACHE_WRITEALLOC #define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -- 2.0.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
