On Mon, 2014-09-15 at 13:05 +0200, ma...@denx.de wrote: > This entire RFC series is the first stab at making SoCFPGA usable with > mainline U-Boot again. There are still some bits missing, but in general, > this allows me to use mainline U-Boot on my SoCFPGA systems. The big > missing part is the SPL generation, which still needs a lot of additional > work. > > This set contains patches for a few subsystems, bu the most part is the > SoCFPGA chip support. > > Most of the patches should be in good shape already, so I wonder if the > RFC tag is really necessary. > > Charles Manning (1): > tools: socfpga: Add socfpga preloader signing to mkimage > > Marek Vasut (21): > net: dwc: Fix cache alignment issues > net: dwc: Make the cache handling less cryptic > mmc: dw_mmc: Fix cache alignment issue > arm: socfpga: Clean up base address file > arm: socfpga: sysmgr: Clean up system manager > arm: socfpga: clock: Implant order into bit definitions > arm: socfpga: clock: Drop nonsense inlining from clock manager code > arm: socfpga: clock: Add missing stubs into board file > arm: socfpga: clock: Trim down code duplication > arm: socfpga: timer: Pull the timer reload value from config file > arm: socfpga: reset: Add EMAC reset functions > arm: socfpga: board: Align checkboard() output > arm: socfpga: reset: Add function to reset FPGA bridges > arm: socfpga: sysmgr: Add FPGA bits into system manager > arm: cache: Add support for write-allocate D-Cache > arm: socfpga: cache: Define cacheline size > arm: socfpga: cache: Enable D-Cache > arm: socfpga: cache: Enable PL310 L2 cache > arm: socfpga: scu: Add SCU register file > arm: socfpga: nic301: Add NIC-301 GPV register file > arm: socfpga: pl310: Map SDRAM to 0x0 > > Pavel Machek (13): > net: Remove unused CONFIG_DW_SEARCH_PHY from configs > net: phy: Cleanup drivers/net/phy/micrel.c > mmc: dw_mmc: cleanups > arm: socfpga: Complete the list of base addresses > arm: socfpga: Add watchdog disable for socfpga > arm: socfpga: clock: Add code to read clock configuration > arm: socfpga: mmc: Pick the clock from clock manager > arm: socfpga: misc: Add proper ethernet initialization > arm: socfpga: misc: Add SD controller init > arm: socfpga: misc: Align print_cpuinfo() output > arm: socfpga: board: Correctly set ATAG position > arm: socfpga: fpga: Add SoCFPGA FPGA programming interface > arm: socfpga: nic301: Add NIC-301 configuration code > > arch/arm/cpu/armv7/socfpga/Makefile | 3 +- > arch/arm/cpu/armv7/socfpga/clock_manager.c | 218 ++++++++++++- > arch/arm/cpu/armv7/socfpga/fpga_manager.c | 354 > +++++++++++++++++++++ > arch/arm/cpu/armv7/socfpga/misc.c | 144 ++++++++- > arch/arm/cpu/armv7/socfpga/reset_manager.c | 72 +++++ > arch/arm/cpu/armv7/socfpga/system_manager.c | 57 +++- > arch/arm/cpu/armv7/socfpga/timer.c | 2 + > arch/arm/include/asm/arch-socfpga/clock_manager.h | 209 ++++++++---- > arch/arm/include/asm/arch-socfpga/fpga_manager.h | 77 +++++ > arch/arm/include/asm/arch-socfpga/nic301.h | 195 ++++++++++++ > arch/arm/include/asm/arch-socfpga/reset_manager.h | 6 + > arch/arm/include/asm/arch-socfpga/scu.h | 23 ++ > .../include/asm/arch-socfpga/socfpga_base_addrs.h | 62 +++- > arch/arm/include/asm/arch-socfpga/system_manager.h | 111 +++++-- > arch/arm/include/asm/system.h | 1 + > arch/arm/lib/cache-cp15.c | 2 + > board/altera/socfpga/pll_config.h | 3 + > board/altera/socfpga/socfpga_cyclone5.c | 7 +- > common/image.c | 1 + > drivers/fpga/altera.c | 21 ++ > drivers/mmc/dw_mmc.c | 26 +- > drivers/mmc/socfpga_dw_mmc.c | 15 +- > drivers/net/designware.c | 46 +-- > drivers/net/phy/micrel.c | 7 +- > include/altera.h | 1 + > include/configs/axs101.h | 1 - > include/configs/socfpga_cyclone5.h | 9 +- > include/dwmmc.h | 2 +- > include/image.h | 1 + > tools/Makefile | 1 + > tools/imagetool.c | 2 + > tools/imagetool.h | 1 + > tools/socfpgaimage.c | 255 +++++++++++++++ > 33 files changed, 1753 insertions(+), 182 deletions(-) > create mode 100644 arch/arm/cpu/armv7/socfpga/fpga_manager.c > create mode 100644 arch/arm/include/asm/arch-socfpga/fpga_manager.h > create mode 100644 arch/arm/include/asm/arch-socfpga/nic301.h > create mode 100644 arch/arm/include/asm/arch-socfpga/scu.h > create mode 100644 tools/socfpgaimage.c > > Cc: Chin Liang See <cl...@altera.com> > Cc: Dinh Nguyen <dingu...@altera.com> > Cc: Albert Aribaud <albert.u.b...@aribaud.net> > Cc: Tom Rini <tr...@ti.com> > Cc: Wolfgang Denk <w...@denx.de> > Cc: Pavel Machek <pa...@denx.de> > Cc: Joe Hershberger <joe.hershber...@gmail.com> >
A quick test from my side and result as below: 1. SDRAM access is working where I can read and write to few spots. :) SOCFPGA_CYCLONE5 # md 0 00000000: 00000000 aaaaaaaa aaaaaaaa aaaaaaaa ................ SOCFPGA_CYCLONE5 # mw 0 12345678 100 SOCFPGA_CYCLONE5 # md 0 00000000: 12345678 12345678 12345678 12345678 xV4.xV4.xV4.xV4. SOCFPGA_CYCLONE5 # md 100000 00100000: eafffffd fbff4b3f fffffffe fdff33be ....?K.......3.. SOCFPGA_CYCLONE5 # mw 100000 23456789 100 SOCFPGA_CYCLONE5 # md 100000 00100000: 23456789 23456789 23456789 23456789 .gE#.gE#.gE#.gE# SOCFPGA_CYCLONE5 # 2. Ethernet seems not working for me. But I will look into this to find out any missing pieces. SOCFPGA_CYCLONE5 # setenv ethaddr 02:11:22:33:44:55 SOCFPGA_CYCLONE5 # dhcp Speed: 1000, full duplex BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4 BOOTP broadcast 5 BOOTP broadcast 6 BOOTP broadcast 7 BOOTP broadcast 8 BOOTP broadcast 9 BOOTP broadcast 10 BOOTP broadcast 11 BOOTP broadcast 12 BOOTP broadcast 13 BOOTP broadcast 14 BOOTP broadcast 15 BOOTP broadcast 16 BOOTP broadcast 17 Retry time exceeded; starting again 3. MMC is not enabled in SocFPGA. I recall there is a patch from Pavel. I believe its pending for v2 due to some comments. Thanks Chin Liang _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
