On 09/16/2014 08:18 AM, Pavel Machek wrote:
> Hi!
>
> On Mon 2014-09-15 13:05:53, Marek Vasut wrote:
>> This entire RFC series is the first stab at making SoCFPGA usable with
>> mainline U-Boot again. There are still some bits missing, but in general,
>> this allows me to use mainline U-Boot on my SoCFPGA systems. The big
>> missing part is the SPL generation, which still needs a lot of additional
>> work.
>>
>> This set contains patches for a few subsystems, bu the most part is the
>> SoCFPGA chip support.
>>
>> Most of the patches should be in good shape already, so I wonder if the
>> RFC tag is really necessary.
>
> Just... I earlier today I tested Marek's git tree based on this
> series, and it works well for me on board similar to sockit.
>
> So
>
> Tested-by: Pavel Machek <pa...@denx.de>
>
> Thanks and best regards,
> Pavel
>
I applied all the patches to v2014.10-rc2, and I see that the watchdog
has been enabled and it's getting reset:
U-Boot 2014.10-rc2-00139-g70e9e3e (Sep 16 2014 - 11:21:38)
CPU: Altera SoCFPGA Platform
BOARD: Altera SoCFPGA Cyclone5 Board
Watchdog enabled
DRAM:
U-Boot SPL 2013.01.01-00019-g9cce15f (Jul 18 2013 - 13:05:43)
SDRAM : Initializing MMR registers
SDRAM : Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
ALTERA DWMMC: 0
reading u-boot.img
reading u-boot.img
U-Boot 2014.10-rc2-00139-g70e9e3e (Sep 16 2014 - 11:21:38)
CPU: Altera SoCFPGA Platform
BOARD: Altera SoCFPGA Cyclone5 Board
Watchdog enabled
DRAM:
This was tested a Cyclone5 devkit.
Dinh
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