Hi, On 3 September 2014 17:37, Simon Glass <s...@chromium.org> wrote:
> This is an implementation of GPIOs for Tegra that uses driver model. It has > been tested on trimslice and also using the new iotrace feature. > > The implementation uses a top-level GPIO device (which has no actual > GPIOS). > Under this all the banks are created as separate GPIO devices. > > The GPIOs are named as per the Tegra datasheet/header files: A0..A7, > B0..B7, > ..., Z0..Z7, AA0..AA7, etc. > > Since driver model is not yet available before relocation, or in SPL, a > special function is provided for seaboard's SPL code. > > Signed-off-by: Simon Glass <s...@chromium.org> > I've tested this series as much as I can, and in particular on Tegra 20, 30 and 124. Are there any final comments before I pull it into dm/master? I'd like to allow plenty of test time before the release. Regards, Simon
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