The clock of SCIF (serial port) of lager is supplied from External Clock. And value of clock is 14.7456MHz.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu...@renesas.com> --- include/configs/lager.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/lager.h b/include/configs/lager.h index f39a788..5f5d107 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -168,7 +168,7 @@ #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ #define CONFIG_SYS_TMU_CLK_DIV 4 -- 2.0.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
