DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination
and this is controlled by gpio7_11. Configuring gpio7_11.
The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards,
and left unused on previous boards, so enabling this gpio for all the
boards, as it is unaffected.
Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com>
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 6 ++++++
arch/arm/include/asm/arch-omap5/gpio.h | 12 ++++++++++++
arch/arm/include/asm/arch-omap5/sys_proto.h | 1 +
board/ti/dra7xx/evm.c | 21 +++++++++++++++++++++
board/ti/dra7xx/mux_data.h | 1 +
5 files changed, 41 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 71c0cc8..74ebf41 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1307,6 +1307,10 @@ static void do_bug0039_workaround(u32 base)
__raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl);
}
+void __weak ddr_regulator_enable(void)
+{
+}
+
/*
* SDRAM initialization:
* SDRAM initialization has two parts:
@@ -1342,6 +1346,8 @@ void sdram_init(void)
bypass_dpll((*prcm)->cm_clkmode_dpll_core);
else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
+
+ ddr_regulator_enable();
}
if (!in_sdram)
diff --git a/arch/arm/include/asm/arch-omap5/gpio.h
b/arch/arm/include/asm/arch-omap5/gpio.h
index 9dd03c9..bd6c835 100644
--- a/arch/arm/include/asm/arch-omap5/gpio.h
+++ b/arch/arm/include/asm/arch-omap5/gpio.h
@@ -34,4 +34,16 @@
#define OMAP54XX_GPIO7_BASE 0x48051000
#define OMAP54XX_GPIO8_BASE 0x48053000
+/* GPIO CTRL register */
+#define GPIO_CTRL_DISABLEMODULE_SHIFT 0
+#define GPIO_CTRL_DISABLEMODULE_MASK (1 << 0)
+#define GPIO_CTRL_ENABLEMODULE GPIO_CTRL_DISABLEMODULE_MASK
+
+/* GPIO OUTPUT ENABLE register */
+#define GPIO_OE_ENABLE(x) (1 << x)
+
+/* GPIO SETDATAOUT register */
+#define GPIO_SETDATAOUT(x) (1 << x)
+#define GPIO_DATAOUT(x) (1 << x)
+
#endif /* _GPIO_OMAP5_H */
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h
b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 1038303..4aceb6e 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -56,6 +56,7 @@ void force_emif_self_refresh(void);
void get_ioregs(const struct ctrl_ioregs **regs);
void srcomp_enable(void);
void setup_warmreset_time(void);
+void ddr_regulator_enable(void);
static inline u32 div_round_up(u32 num, u32 den)
{
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 7f19655..ededa1f 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -16,6 +16,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
+#include <asm/arch/gpio.h>
#include <environment.h>
#include "mux_data.h"
@@ -267,3 +268,23 @@ int board_eth_init(bd_t *bis)
return ret;
}
#endif
+
+/* VTT regulator enable */
+void ddr_regulator_enable(void)
+{
+ u32 temp;
+
+ /* Do not enable VTT for DRA722 */
+ if (omap_revision() == DRA722_ES1_0)
+ return;
+
+ /* enable module */
+ writel(GPIO_CTRL_ENABLEMODULE, OMAP54XX_GPIO7_BASE + OMAP_GPIO_CTRL);
+
+ /*enable output for GPIO7_11*/
+ writel(GPIO_SETDATAOUT(11), OMAP54XX_GPIO7_BASE + OMAP_GPIO_SETDATAOUT);
+ temp = readl(OMAP54XX_GPIO7_BASE + OMAP_GPIO_OE);
+ temp = temp & ~(GPIO_OE_ENABLE(11));
+ writel(temp, OMAP54XX_GPIO7_BASE + OMAP_GPIO_OE);
+ writel(GPIO_DATAOUT(11), OMAP54XX_GPIO7_BASE + OMAP_GPIO_DATAOUT);
+}
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index c9e202a..bc17936 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -67,5 +67,6 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
{GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
{USB2_DRVVBUS, (M0 | IEN | FSC) },
+ {SPI1_CS1, (PEN | IDIS | M14) },
};
#endif /* _MUX_DATA_DRA7XX_H_ */
--
1.9.1
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