On Mon, Jun 23, 2014 at 9:53 AM, Fabio Estevam <feste...@gmail.com> wrote:
> From: Fabio Estevam <fabio.este...@freescale.com>
>
> mx6solox is the newest member of the mx6 family.
>
> Some of the new features on this variants are:
> - Cortex M4 microcontroller (besides the CortexA9)
> - Dual Gigabit Ethernet
>
> Add the initial support for it.
>
> Signed-off-by: Fabio Estevam <fabio.este...@freescale.com>
> ---
> Changes since v2:
> - Improve commit log
> - Use is_cpu_type() when possible
>
> arch/arm/cpu/armv7/mx6/clock.c | 11 +-
> arch/arm/cpu/armv7/mx6/soc.c | 26 +++++
> arch/arm/imx-common/cpu.c | 2 +
> arch/arm/include/asm/arch-imx/cpu.h | 3 +-
> arch/arm/include/asm/arch-mx6/crm_regs.h | 170
> ++++++++++++++++++++++++++++++
> arch/arm/include/asm/arch-mx6/imx-regs.h | 122 ++++++++++++++++++++-
> arch/arm/include/asm/arch-mx6/mx6-ddr.h | 4 +
> arch/arm/include/asm/arch-mx6/mx6sx-ddr.h | 45 ++++++++
> 8 files changed, 373 insertions(+), 10 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-mx6/mx6sx-ddr.h
>
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
> index bd65a08..25bee6c 100644
> --- a/arch/arm/cpu/armv7/mx6/clock.c
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -214,10 +214,11 @@ static u32 get_uart_clk(void)
> u32 reg, uart_podf;
> u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
> reg = __raw_readl(&imx_ccm->cscdr1);
> -#ifdef CONFIG_MX6SL
> - if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
> - freq = MXC_HCLK;
> -#endif
> +
> + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6SX))
> + if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
> + freq = MXC_HCLK;
> +
typo, lacks SL support now.
> reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
> uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
>
> @@ -282,7 +283,7 @@ static u32 get_emi_slow_clk(void)
> return root_freq / (emi_slow_podf + 1);
> }
>
> -#ifdef CONFIG_MX6SL
> +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
> static u32 get_mmdc_ch0_clk(void)
> {
> u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index 1725279..e394e3f 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -79,9 +79,15 @@ u32 __weak get_board_rev(void)
> void init_aips(void)
> {
> struct aipstz_regs *aips1, *aips2;
> +#ifdef CONFIG_MX6SX
> + struct aipstz_regs *aips3;
> +#endif
>
> aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
> aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
> +#ifdef CONFIG_MX6SX
> + aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
> +#endif
>
> /*
> * Set all MPROTx to be non-bufferable, trusted for R/W,
> @@ -107,6 +113,26 @@ void init_aips(void)
> writel(0x00000000, &aips2->opacr2);
> writel(0x00000000, &aips2->opacr3);
> writel(0x00000000, &aips2->opacr4);
> +
> +#ifdef CONFIG_MX6SX
> + /*
> + * Set all MPROTx to be non-bufferable, trusted for R/W,
> + * not forced to user-mode.
> + */
> + writel(0x77777777, &aips3->mprot0);
> + writel(0x77777777, &aips3->mprot1);
> +
> + /*
> + * Set all OPACRx to be non-bufferable, not require
> + * supervisor privilege level for access,allow for
> + * write access and untrusted master access.
> + */
> + writel(0x00000000, &aips3->opacr0);
> + writel(0x00000000, &aips3->opacr1);
> + writel(0x00000000, &aips3->opacr2);
> + writel(0x00000000, &aips3->opacr3);
> + writel(0x00000000, &aips3->opacr4);
> +#endif
> }
>
> static void clear_ldo_ramp(void)
> diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
> index 5a09107..7bb0e83 100644
> --- a/arch/arm/imx-common/cpu.c
> +++ b/arch/arm/imx-common/cpu.c
> @@ -112,6 +112,8 @@ const char *get_imx_type(u32 imxtype)
> return "6SOLO"; /* Solo version of the mx6 */
> case MXC_CPU_MX6SL:
> return "6SL"; /* Solo-Lite version of the mx6 */
> + case MXC_CPU_MX6SX:
> + return "6SX"; /* SoloX version of the mx6 */
> case MXC_CPU_MX51:
> return "51";
> case MXC_CPU_MX53:
> diff --git a/arch/arm/include/asm/arch-imx/cpu.h
> b/arch/arm/include/asm/arch-imx/cpu.h
> index a35940e..a3cc96f 100644
> --- a/arch/arm/include/asm/arch-imx/cpu.h
> +++ b/arch/arm/include/asm/arch-imx/cpu.h
> @@ -8,6 +8,7 @@
> #define MXC_CPU_MX53 0x53
> #define MXC_CPU_MX6SL 0x60
> #define MXC_CPU_MX6DL 0x61
> -#define MXC_CPU_MX6SOLO 0x62
> +#define MXC_CPU_MX6SX 0x62
> #define MXC_CPU_MX6Q 0x63
> #define MXC_CPU_MX6D 0x64
> +#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
> diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h
> b/arch/arm/include/asm/arch-mx6/crm_regs.h
> index 7202073..0fcef69 100644
> --- a/arch/arm/include/asm/arch-mx6/crm_regs.h
> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
> @@ -113,7 +113,11 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
> #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
> #define MXC_CCM_CCR_COSC_EN (1 << 12)
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CCR_OSCNT_MASK 0x7F
> +#else
> #define MXC_CCM_CCR_OSCNT_MASK 0xFF
> +#endif
> #define MXC_CCM_CCR_OSCNT_OFFSET 0
>
> /* Define the bits in register CCDR */
> @@ -146,8 +150,10 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
> #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
> #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
> #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
> +#endif
> #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
> #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
> #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
> @@ -173,28 +179,40 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
> #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
> #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
> #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
> #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
> #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
> +#endif
> #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
> #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
> +#endif
> #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
> #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
> #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
> #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
> #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
> #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
> +#endif
>
> /* Define the bits in register CSCMR1 */
> #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
> #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
> +#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
> +#else
> #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
> #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
> +#endif
> #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
> #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
> +/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
> #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
> #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
> #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
> @@ -207,19 +225,38 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
> #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
> #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
> +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
> +#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
> +#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
> +#endif
> #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
>
> /* Define the bits in register CSCMR2 */
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
> +#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
> +#endif
> #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
> #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
> #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
> #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
> +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
> +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
> +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
> +#else
> #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
> #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
> +#endif
>
> /* Define the bits in register CSCDR1 */
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
> #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
> +#endif
> #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
> #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
> #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
> @@ -228,21 +265,28 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
> #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
> #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
> #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
> #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
> #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
> +#endif
> #ifdef CONFIG_MX6SL
> #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F
> #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
> #else
> #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
> +#endif
> #endif
> #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
>
> /* Define the bits in register CS1CDR */
> #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
> #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
> +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
> +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
> #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
> #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
> #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
> @@ -253,6 +297,17 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
>
> /* Define the bits in register CS2CDR */
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
> +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
> +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f)
> << 21)
> +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
> +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
> +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7)
> << 18)
> +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
> +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
> +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7)
> << 15)
> +#else
> #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
> #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
> #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f)
> << 21)
> @@ -262,6 +317,7 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
> #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
> #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16)
> +#endif
> #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
> #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
> #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
> @@ -272,9 +328,11 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
>
> /* Define the bits in register CDCDR */
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
> #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
> #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
> +#endif
> #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
> #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
> #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
> @@ -289,6 +347,20 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
>
> /* Define the bits in register CHSCCDR */
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
> +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
> +#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
> +#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
> +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
> +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
> +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
> +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
> +#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
> +#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
> +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
> +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
> +#else
> #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
> #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
> #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
> @@ -301,6 +373,7 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
> #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
> #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
> +#endif
>
> #define CHSCCDR_CLK_SEL_LDB_DI0 3
> #define CHSCCDR_PODF_DIVIDE_BY_3 2
> @@ -309,12 +382,14 @@ struct mxc_ccm_reg {
> /* Define the bits in register CSCDR2 */
> #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
> #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
> +/* All IPU2_DI1 are LCDIF1 on MX6SX */
> #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
> #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
> #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
> #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
> #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
> #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
> +/* All IPU2_DI0 are LCDIF2 on MX6SX */
> #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
> #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
> #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
> @@ -335,7 +410,9 @@ struct mxc_ccm_reg {
> /* Define the bits in register CDHIPR */
> #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
> #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
> +#endif
> #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
> #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
> #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
> @@ -344,13 +421,17 @@ struct mxc_ccm_reg {
> /* Define the bits in register CLPCR */
> #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
> #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
> #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
> #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
> +#endif
> #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
> #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
> #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
> +#endif
> #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
> #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
> #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
> @@ -359,15 +440,19 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
> #define MXC_CCM_CLPCR_SBYOS (1 << 6)
> #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
> #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
> #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
> +#endif
> #define MXC_CCM_CLPCR_LPM_MASK 0x3
> #define MXC_CCM_CLPCR_LPM_OFFSET 0
>
> /* Define the bits in register CISR */
> #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
> +#endif
> #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
> #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
> #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
> @@ -378,7 +463,9 @@ struct mxc_ccm_reg {
>
> /* Define the bits in register CIMR */
> #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
> +#endif
> #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
> #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
> #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
> @@ -393,6 +480,7 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
> #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
> #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
> +#define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
> #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
> #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
> #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
> @@ -400,6 +488,7 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
>
> /* Define the bits in registers CGPR */
> +#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
> #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
> #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
> #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
> @@ -435,8 +524,13 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCGR0_DCIC1_MASK (3 <<
> MXC_CCM_CCGR0_DCIC1_OFFSET)
> #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
> #define MXC_CCM_CCGR0_DCIC2_MASK (3 <<
> MXC_CCM_CCGR0_DCIC2_OFFSET)
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
> +#define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 <<
> MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
> +#else
> #define MXC_CCM_CCGR0_DTCP_OFFSET 28
> #define MXC_CCM_CCGR0_DTCP_MASK (3 <<
> MXC_CCM_CCGR0_DTCP_OFFSET)
> +#endif
>
> #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
> #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 <<
> MXC_CCM_CCGR1_ECSPI1S_OFFSET)
> @@ -448,27 +542,48 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 <<
> MXC_CCM_CCGR1_ECSPI4S_OFFSET)
> #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
> #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 <<
> MXC_CCM_CCGR1_ECSPI5S_OFFSET)
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
> #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 <<
> MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
> +#endif
> #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
> #define MXC_CCM_CCGR1_EPIT1S_MASK (3 <<
> MXC_CCM_CCGR1_EPIT1S_OFFSET)
> #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
> #define MXC_CCM_CCGR1_EPIT2S_MASK (3 <<
> MXC_CCM_CCGR1_EPIT2S_OFFSET)
> #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
> #define MXC_CCM_CCGR1_ESAIS_MASK (3 <<
> MXC_CCM_CCGR1_ESAIS_OFFSET)
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
> +#define MXC_CCM_CCGR1_WAKEUP_MASK (3 <<
> MXC_CCM_CCGR1_WAKEUP_OFFSET)
> +#endif
> #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
> #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 <<
> MXC_CCM_CCGR1_GPT_BUS_OFFSET)
> #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
> #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 <<
> MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
> #define MXC_CCM_CCGR1_GPU2D_MASK (3 <<
> MXC_CCM_CCGR1_GPU2D_OFFSET)
> +#endif
> #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
> #define MXC_CCM_CCGR1_GPU3D_MASK (3 <<
> MXC_CCM_CCGR1_GPU3D_OFFSET)
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
> +#define MXC_CCM_CCGR1_OCRAM_S_MASK (3 <<
> MXC_CCM_CCGR1_OCRAM_S_OFFSET)
> +#define MXC_CCM_CCGR1_CANFD_OFFSET 30
> +#define MXC_CCM_CCGR1_CANFD_MASK (3 <<
> MXC_CCM_CCGR1_CANFD_OFFSET)
> +#endif
>
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
> #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 <<
> MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
> +#else
> +#define MXC_CCM_CCGR2_CSI_OFFSET 2
> +#define MXC_CCM_CCGR2_CSI_MASK (3 <<
> MXC_CCM_CCGR2_CSI_OFFSET)
> +#endif
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
> #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 <<
> MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
> +#endif
> #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
> #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 <<
> MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
> #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
> @@ -487,17 +602,33 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCGR2_IPMUX3_MASK (3 <<
> MXC_CCM_CCGR2_IPMUX3_OFFSET)
> #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
> #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 <<
> MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CCGR2_LCD_OFFSET 28
> +#define MXC_CCM_CCGR2_LCD_MASK (3 <<
> MXC_CCM_CCGR2_LCD_OFFSET)
> +#define MXC_CCM_CCGR2_PXP_OFFSET 30
> +#define MXC_CCM_CCGR2_PXP_MASK (3 <<
> MXC_CCM_CCGR2_PXP_OFFSET)
> +#else
> #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
> #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 <<
> MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
> #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
> #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 <<
> MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
> +#endif
>
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CCGR3_M4_OFFSET 2
> +#define MXC_CCM_CCGR3_M4_MASK (3 <<
> MXC_CCM_CCGR3_M4_OFFSET)
> +#define MXC_CCM_CCGR3_ENET_OFFSET 4
> +#define MXC_CCM_CCGR3_ENET_MASK (3 <<
> MXC_CCM_CCGR3_ENET_OFFSET)
> +#define MXC_CCM_CCGR3_QSPI_OFFSET 14
> +#define MXC_CCM_CCGR3_QSPI_MASK (3 <<
> MXC_CCM_CCGR3_QSPI_OFFSET)
> +#else
> #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
> #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 <<
> MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
> #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
> #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 <<
> MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
> #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
> #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 <<
> MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
> +#endif
> #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
> #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 <<
> MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
> #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
> @@ -506,29 +637,43 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 <<
> MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
> #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
> #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 <<
> MXC_CCM_CCGR3_LDB_DI0_OFFSET)
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CCGR3_QSPI1_OFFSET 14
> +#define MXC_CCM_CCGR3_QSPI1_MASK (3 <<
> MXC_CCM_CCGR3_QSPI1_OFFSET)
> +#else
> #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
> #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 <<
> MXC_CCM_CCGR3_LDB_DI1_OFFSET)
> #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
> #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 <<
> MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
> +#endif
> #define MXC_CCM_CCGR3_MLB_OFFSET 18
> #define MXC_CCM_CCGR3_MLB_MASK (3 <<
> MXC_CCM_CCGR3_MLB_OFFSET)
> #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
> #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 <<
> MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
> #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 <<
> MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
> +#endif
> #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
> #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 <<
> MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
> #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
> #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 <<
> MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
> #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
> #define MXC_CCM_CCGR3_OCRAM_MASK (3 <<
> MXC_CCM_CCGR3_OCRAM_OFFSET)
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
> #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 <<
> MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
> +#endif
>
> #define MXC_CCM_CCGR4_PCIE_OFFSET 0
> #define MXC_CCM_CCGR4_PCIE_MASK (3 <<
> MXC_CCM_CCGR4_PCIE_OFFSET)
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
> +#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 <<
> MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
> +#else
> #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
> #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 <<
> MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
> +#endif
> #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
> #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 <<
> MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
> #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
> @@ -552,8 +697,10 @@ struct mxc_ccm_reg {
>
> #define MXC_CCM_CCGR5_ROM_OFFSET 0
> #define MXC_CCM_CCGR5_ROM_MASK (3 <<
> MXC_CCM_CCGR5_ROM_OFFSET)
> +#ifndef CONFIG_MX6SX
> #define MXC_CCM_CCGR5_SATA_OFFSET 4
> #define MXC_CCM_CCGR5_SATA_MASK (3 <<
> MXC_CCM_CCGR5_SATA_OFFSET)
> +#endif
> #define MXC_CCM_CCGR5_SDMA_OFFSET 6
> #define MXC_CCM_CCGR5_SDMA_MASK (3 <<
> MXC_CCM_CCGR5_SDMA_OFFSET)
> #define MXC_CCM_CCGR5_SPBA_OFFSET 12
> @@ -570,6 +717,12 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCGR5_UART_MASK (3 <<
> MXC_CCM_CCGR5_UART_OFFSET)
> #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
> #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 <<
> MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CCGR5_SAI1_OFFSET 20
> +#define MXC_CCM_CCGR5_SAI1_MASK (3 <<
> MXC_CCM_CCGR5_SAI1_OFFSET)
> +#define MXC_CCM_CCGR5_SAI2_OFFSET 30
> +#define MXC_CCM_CCGR5_SAI2_MASK (3 <<
> MXC_CCM_CCGR5_SAI2_OFFSET)
> +#endif
>
> #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
> #define MXC_CCM_CCGR6_USBOH3_MASK (3 <<
> MXC_CCM_CCGR6_USBOH3_OFFSET)
> @@ -583,8 +736,25 @@ struct mxc_ccm_reg {
> #define MXC_CCM_CCGR6_USDHC4_MASK (3 <<
> MXC_CCM_CCGR6_USDHC4_OFFSET)
> #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
> #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 <<
> MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
> +#ifdef CONFIG_MX6SX
> +#define MXC_CCM_CCGR6_PWM8_OFFSET 16
> +#define MXC_CCM_CCGR6_PWM8_MASK (3 <<
> MXC_CCM_CCGR6_PWM8_OFFSET)
> +#define MXC_CCM_CCGR6_VADC_OFFSET 20
> +#define MXC_CCM_CCGR6_VADC_MASK (3 <<
> MXC_CCM_CCGR6_VADC_OFFSET)
> +#define MXC_CCM_CCGR6_GIS_OFFSET 22
> +#define MXC_CCM_CCGR6_GIS_MASK (3 <<
> MXC_CCM_CCGR6_GIS_OFFSET)
> +#define MXC_CCM_CCGR6_I2C4_OFFSET 24
> +#define MXC_CCM_CCGR6_I2C4_MASK (3 <<
> MXC_CCM_CCGR6_I2C4_OFFSET)
> +#define MXC_CCM_CCGR6_PWM5_OFFSET 26
> +#define MXC_CCM_CCGR6_PWM5_MASK (3 <<
> MXC_CCM_CCGR6_PWM5_OFFSET)
> +#define MXC_CCM_CCGR6_PWM6_OFFSET 28
> +#define MXC_CCM_CCGR6_PWM6_MASK (3 <<
> MXC_CCM_CCGR6_PWM6_OFFSET)
> +#define MXC_CCM_CCGR6_PWM7_OFFSET 30
> +#define MXC_CCM_CCGR6_PWM7_MASK (3 <<
> MXC_CCM_CCGR6_PWM7_OFFSET)
> +#else
> #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
> #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 <<
> MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
> +#endif
>
> #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
> #define BP_ANADIG_PLL_SYS_RSVD0 20
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
> b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index 1f19727..b47e039 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -19,6 +19,19 @@
> #define GPU_2D_ARB_END_ADDR 0x02203FFF
> #define OPENVG_ARB_BASE_ADDR 0x02204000
> #define OPENVG_ARB_END_ADDR 0x02207FFF
> +#elif CONFIG_MX6SX
> +#define CAAM_ARB_BASE_ADDR 0x00100000
> +#define CAAM_ARB_END_ADDR 0x00107FFF
> +#define GPU_ARB_BASE_ADDR 0x01800000
> +#define GPU_ARB_END_ADDR 0x01803FFF
> +#define APBH_DMA_ARB_BASE_ADDR 0x01804000
> +#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
> +#define M4_BOOTROM_BASE_ADDR 0x007F8000
> +
> +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
> +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
> +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
> +
> #else
> #define CAAM_ARB_BASE_ADDR 0x00100000
> #define CAAM_ARB_END_ADDR 0x00103FFF
> @@ -39,14 +52,27 @@
> #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
>
> /* GPV - PL301 configuration ports */
> -#ifdef CONFIG_MX6SL
> +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
> #define GPV2_BASE_ADDR 0x00D00000
> #else
> #define GPV2_BASE_ADDR 0x00200000
> #endif
>
> +#ifdef CONFIG_MX6SX
> +#define GPV3_BASE_ADDR 0x00E00000
> +#define GPV4_BASE_ADDR 0x00F00000
> +#define GPV5_BASE_ADDR 0x01000000
> +#define GPV6_BASE_ADDR 0x01100000
> +#define PCIE_ARB_BASE_ADDR 0x08000000
> +#define PCIE_ARB_END_ADDR 0x08FFFFFF
> +
> +#else
> #define GPV3_BASE_ADDR 0x00300000
> #define GPV4_BASE_ADDR 0x00800000
> +#define PCIE_ARB_BASE_ADDR 0x01000000
> +#define PCIE_ARB_END_ADDR 0x01FFFFFF
> +#endif
> +
> #define IRAM_BASE_ADDR 0x00900000
> #define SCU_BASE_ADDR 0x00A00000
> #define IC_INTERFACES_BASE_ADDR 0x00A00100
> @@ -56,13 +82,21 @@
> #define L2_PL310_BASE 0x00A02000
> #define GPV0_BASE_ADDR 0x00B00000
> #define GPV1_BASE_ADDR 0x00C00000
> -#define PCIE_ARB_BASE_ADDR 0x01000000
> -#define PCIE_ARB_END_ADDR 0x01FFFFFF
>
> #define AIPS1_ARB_BASE_ADDR 0x02000000
> #define AIPS1_ARB_END_ADDR 0x020FFFFF
> #define AIPS2_ARB_BASE_ADDR 0x02100000
> #define AIPS2_ARB_END_ADDR 0x021FFFFF
> +#ifdef CONFIG_MX6SX
> +#define AIPS3_BASE_ADDR 0x02200000
> +#define AIPS3_END_ADDR 0x022FFFFF
> +#define WEIM_ARB_BASE_ADDR 0x50000000
> +#define WEIM_ARB_END_ADDR 0x57FFFFFF
> +#define QSPI1_ARB_BASE_ADDR 0x60000000
> +#define QSPI1_ARB_END_ADDR 0x6FFFFFFF
> +#define QSPI2_ARB_BASE_ADDR 0x70000000
> +#define QSPI2_ARB_END_ADDR 0x7FFFFFFF
> +#else
> #define SATA_ARB_BASE_ADDR 0x02200000
> #define SATA_ARB_END_ADDR 0x02203FFF
> #define OPENVG_ARB_BASE_ADDR 0x02204000
> @@ -75,8 +109,9 @@
> #define IPU2_ARB_END_ADDR 0x02BFFFFF
> #define WEIM_ARB_BASE_ADDR 0x08000000
> #define WEIM_ARB_END_ADDR 0x0FFFFFFF
> +#endif
>
> -#ifdef CONFIG_MX6SL
> +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
> #define MMDC0_ARB_BASE_ADDR 0x80000000
> #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
> #define MMDC1_ARB_BASE_ADDR 0xC0000000
> @@ -88,8 +123,10 @@
> #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
> #endif
>
> +#ifndef CONFIG_MX6SX
> #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
> #define IPU_SOC_OFFSET 0x00200000
> +#endif
>
> /* Defines for Blocks connected via AIPS (SkyBlue) */
> #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
> @@ -112,7 +149,9 @@
> #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
> #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
> #else
> +#ifndef CONFIG_MX6SX
> #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
> +#endif
> #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
> #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
> #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
> @@ -121,8 +160,10 @@
> #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
> #endif
>
> +#ifndef CONFIG_MX6SX
> #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
> #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
> +#endif
> #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
>
> #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
> @@ -157,6 +198,13 @@
> #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
> #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
> #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
> +#elif CONFIG_MX6SX
> +#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
> +#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
> +#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
> +#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
> +#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
> +#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
> #else
> #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
> #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
> @@ -193,6 +241,8 @@
> #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
> #ifdef CONFIG_MX6SL
> #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
> +#elif CONFIG_MX6SX
> +#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
> #else
> #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
> #endif
> @@ -202,13 +252,28 @@
> #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
> #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
> #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
> +#ifdef CONFIG_MX6SX
> +#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
> +#else
> #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
> +#endif
> #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
> +#ifdef CONFIG_MX6SX
> +#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
> +#else
> #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
> +#endif
> #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
> +#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
> +#ifdef CONFIG_MX6SX
> +#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
> +#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
> +#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
> +#else
> #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
> #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
> #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
> +#endif
> #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
> #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
> #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
> @@ -216,8 +281,40 @@
> #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
> #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
>
> +#ifdef CONFIG_MX6SX
> +#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
> +#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
> +#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
> +#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
> +#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
> +#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
> +#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
> +#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
> +#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
> +#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
> +#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
> +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
> +#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
> +#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
> +#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
> +#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
> +#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
> +#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
> +#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
> +#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
> +#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
> +#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
> +#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
> +#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
> +#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
> +#endif
> +
> #define CHIP_REV_1_0 0x10
> +#ifndef CONFIG_MX6SX
> #define IRAM_SIZE 0x00040000
> +#else
> +#define IRAM_SIZE 0x00020000
> +#endif
> #define FEC_QUIRK_ENET_MAC
>
> #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
> @@ -471,6 +568,22 @@ struct fuse_bank0_regs {
> u32 rsvd7[4];
> };
>
> +#ifdef CONFIG_MX6SX
> +struct fuse_bank4_regs {
> + u32 sjc_resp_low;
> + u32 rsvd0[3];
> + u32 sjc_resp_high;
> + u32 rsvd1[3];
> + u32 mac_addr_low;
> + u32 rsvd2[3];
> + u32 mac_addr_high;
> + u32 rsvd3[3];
> + u32 mac_addr2;
> + u32 rsvd4[7];
> + u32 gp1;
> + u32 rsvd5[7];
> +};
> +#else
> struct fuse_bank4_regs {
> u32 sjc_resp_low;
> u32 rsvd0[3];
> @@ -485,6 +598,7 @@ struct fuse_bank4_regs {
> u32 gp2;
> u32 rsvd5[3];
> };
> +#endif
>
> struct aipstz_regs {
> u32 mprot0;
> diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> index d544d2e..5ebabfa 100644
> --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> @@ -13,7 +13,11 @@
> #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
> #include "mx6dl-ddr.h"
> #else
> +#ifdef CONFIG_MX6SX
> +#include "mx6sx-ddr.h"
> +#else
> #error "Please select cpu"
> +#endif /* CONFIG_MX6SX */
> #endif /* CONFIG_MX6DL or CONFIG_MX6S */
> #endif /* CONFIG_MX6Q */
> #else
> diff --git a/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h
> b/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h
> new file mode 100644
> index 0000000..2cc94aa
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h
> @@ -0,0 +1,45 @@
> +/*
> + * Copyright (C) 2014 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __ASM_ARCH_MX6SX_DDR_H__
> +#define __ASM_ARCH_MX6SX_DDR_H__
> +
> +#ifndef CONFIG_MX6SX
> +#error "wrong CPU"
> +#endif
> +
> +#define MX6_IOM_DRAM_DQM0 0x020e02ec
> +#define MX6_IOM_DRAM_DQM1 0x020e02f0
> +#define MX6_IOM_DRAM_DQM2 0x020e02f4
> +#define MX6_IOM_DRAM_DQM3 0x020e02f8
> +
> +#define MX6_IOM_DRAM_RAS 0x020e02fc
> +#define MX6_IOM_DRAM_CAS 0x020e0300
> +#define MX6_IOM_DRAM_SDODT0 0x020e0310
> +#define MX6_IOM_DRAM_SDODT1 0x020e0314
> +#define MX6_IOM_DRAM_SDBA2 0x020e0320
> +#define MX6_IOM_DRAM_SDCKE0 0x020e0324
> +#define MX6_IOM_DRAM_SDCKE1 0x020e0328
> +#define MX6_IOM_DRAM_SDCLK_0 0x020e032c
> +#define MX6_IOM_DRAM_RESET 0x020e0340
> +
> +#define MX6_IOM_DRAM_SDQS0 0x020e0330
> +#define MX6_IOM_DRAM_SDQS1 0x020e0334
> +#define MX6_IOM_DRAM_SDQS2 0x020e0338
> +#define MX6_IOM_DRAM_SDQS3 0x020e033c
> +
> +#define MX6_IOM_GRP_ADDDS 0x020e05f4
> +#define MX6_IOM_DDRMODE_CTL 0x020e05f8
> +#define MX6_IOM_GRP_DDRPKE 0x020e05fc
> +#define MX6_IOM_GRP_DDRMODE 0x020e0608
> +#define MX6_IOM_GRP_B0DS 0x020e060c
> +#define MX6_IOM_GRP_B1DS 0x020e0610
> +#define MX6_IOM_GRP_CTLDS 0x020e0614
> +#define MX6_IOM_GRP_DDR_TYPE 0x020e0618
> +#define MX6_IOM_GRP_B2DS 0x020e061c
> +#define MX6_IOM_GRP_B3DS 0x020e0620
> +
> +#endif /*__ASM_ARCH_MX6SX_DDR_H__ */
> --
> 1.8.3.2
>
> _______________________________________________
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> U-Boot@lists.denx.de
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--
Otavio Salvador O.S. Systems
http://www.ossystems.com.br http://code.ossystems.com.br
Mobile: +55 (53) 9981-7854 Mobile: +1 (347) 903-9750
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