On Sunday, April 13, 2014 at 09:55:57 PM, Ian Campbell wrote: > On Mon, 2014-03-24 at 23:42 +0100, Olliver Schinagl wrote: > > On 03/24/2014 09:52 PM, Marek Vasut wrote: > > >> + /* Switch to 24MHz clock while changing PLL1 */ > > >> + writel(AXI_DIV_1 << AXI_DIV_SHIFT | > > >> + AHB_DIV_2 << AHB_DIV_SHIFT | > > >> + APB0_DIV_1 << APB0_DIV_SHIFT | > > >> + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, > > >> + &ccm->cpu_ahb_apb0_cfg); > > >> + sdelay(20); > > > > > > What is sdelay() function all about ? > > > > It also is from > > arch/arm/include/asm/arch-sunxi/sys_proto.h > > and I thought all where replaced with udelays > > Since these sdelays() are used while we are frobbing around with the > clocks I'm not sure that switching to udelay is possible/wise. sdelay is > documented as: > * sdelay() - simple spin loop. Will be constant time as > * its generally used in bypass conditions only. This > * is necessary until timers are accessible. > > IOW it sounds like it is designed to be used in exactly these > circumstances. > > Given the lack of documentation for what is actually required by the > hardware when changing these clocks I'm a bit reluctant to go changing > things.
Don't you have an clock-agnostic timer in the chip ? If not, well, can't be helped. Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
