On Monday, March 24, 2014 at 11:42:17 PM, Olliver Schinagl wrote: > On 03/24/2014 09:52 PM, Marek Vasut wrote: > > On Friday, March 21, 2014 at 10:54:18 PM, Ian Campbell wrote: > >> This has been stripped back for mainlining and supports only sun7i. > >> These changes are not useful by themselves but are split out to make > >> the patch sizes more manageable. > > > > [...] > > > >> +int clock_init(void) > >> +{ > >> + struct sunxi_ccm_reg *const ccm = > >> + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; > >> + > >> +#ifdef CONFIG_SPL_BUILD > >> + clock_init_safe(); > >> +#endif > >> + > >> + /* uart clock source is apb1 */ > >> + sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M); > >> + sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N); > >> + sr32(&ccm->apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M); > > > > sr32() is not defined anywhere. > > it should be defined in > arch/arm/include/asm/arch-sunxi/sys_proto.h > and comes from > arch/arm/cpu/armv7/syslib.c > > it was added for the ti omap's > > I've got a local cleanup patch set where I fixed this already to > clrsetbits_le32
It's not part of this patch, but then, use clrsetbits_le32() instead of course. > >> + /* open the clock for uart */ > >> + sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN); > >> + > >> + return 0; > >> +} > >> + > >> +/* Return PLL5 frequency in Hz > >> + * Note: Assumes PLL5 reference is 24MHz clock > >> + */ > >> +unsigned int clock_get_pll5(void) > >> +{ > >> + struct sunxi_ccm_reg *const ccm = > >> + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; > >> + uint32_t rval = readl(&ccm->pll5_cfg); > >> + int n = (rval >> 8) & 0x1f; > >> + int k = ((rval >> 4) & 3) + 1; > >> + int p = 1 << ((rval >> 16) & 3); > >> + return 24000000 * n * k / p; > > > > Please fix the magic values here. > > [...] > > Same here, got that in my local tree too Then make it part of the V3 please. [...] _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot