This patch add support for one device of the Bachmann OT1200
series - the mr variant.
My first attemp was to use one u-boot binary for all OT1200
devices, but as I need to load a device-specific devicetree
I decided to go this way.
Following components are used:
+ ethernet
+ usb
+ i2c
+ display connected via ldb (init and usage in linux only)
+ emmc
Signed-off-by: Christian Gmeiner <christian.gmei...@gmail.com>
---
board/bachmann/ot1200/Makefile | 9 ++
board/bachmann/ot1200/ot1200.c | 246 ++++++++++++++++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/ot1200.h | 241 +++++++++++++++++++++++++++++++++++++++
4 files changed, 497 insertions(+)
create mode 100644 board/bachmann/ot1200/Makefile
create mode 100644 board/bachmann/ot1200/ot1200.c
create mode 100644 include/configs/ot1200.h
diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile
new file mode 100644
index 0000000..1bd42e8
--- /dev/null
+++ b/board/bachmann/ot1200/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <l...@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Boundary Devices <i...@boundarydevices.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := ot1200.o
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
new file mode 100644
index 0000000..6a884c2
--- /dev/null
+++ b/board/bachmann/ot1200/ot1200.c
@@ -0,0 +1,246 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Bachmann electronic GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <pca953x.h>
+#include <edid.h>
+#include <linux/fb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_GPIO_16__ENET_ETHERNET_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD0__ENET_RDATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD1__ENET_RDATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_COL2__ENET_RDATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_COL0__ENET_RDATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TXD0__ENET_TDATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TXD1__ENET_TDATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_ROW2__ENET_TDATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__ENET_TDATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_enet();
+ return 0;
+}
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+void setup_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_RST__USDHC3_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
+
+struct fsl_esdhc_cfg usdhc_cfg[] = {
+ {USDHC3_BASE_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[0].max_bus_width = 8;
+
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C2 - EDID */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO_2_30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D16__GPIO_3_16 | PC,
+ .gp = IMX_GPIO_NR(3, 16)
+ }
+};
+
+/* I2C3 - IO expander */
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D17__GPIO_3_17 | PC,
+ .gp = IMX_GPIO_NR(3, 17)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO_3_18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+static iomux_v3_cfg_t const pwm_pad[] = {
+ MX6_PAD_SD1_CMD__PWM4_PWMO | MUX_PAD_CTRL(OUTPUT_40OHM),
+};
+
+static void leds_on(void)
+{
+ i2c_set_bus_num(2);
+ pca953x_set_dir(0x20, 0xffff, PCA953X_DIR_OUT);
+ pca953x_set_val(0x20, 0xffff, 0x0);
+}
+
+static void backlight_off(void)
+{
+ unsigned gpio = IMX_GPIO_NR(2, 0);
+ //gpio_direction_input(gpio);
+ gpio_direction_output(gpio, 0);
+ //gpio_set_value(gpio, 0);
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ struct edid1_info edid;
+ struct fb_videomode mode;
+
+ i2c_set_bus_num(1);
+ if (i2c_read(0x52, 0, 1, (uchar *)&edid, sizeof(edid)) != 0) {
+ puts("Error reading EDID content.\n");
+ return;
+ }
+
+ if (edid_check_info(&edid)) {
+ puts("Content isn't valid EDID.\n");
+ return;
+ }
+
+ edid_to_fb_videomode(&edid, &mode);
+
+ /* find display-timings node */
+ int noff = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-ldb");
+ int channel = fdt_subnode_offset(blob, noff, "lvds-channel"); //
lvds-channel@0
+ int timings = fdt_subnode_offset(blob, channel, "display-timings");
+
+ /* clean-up all the mess */
+ fdt_del_node(blob, timings);
+ fdt_add_subnode(blob, channel, "display-timings");
+ timings = fdt_subnode_offset(blob, channel, "display-timings");
+ int final = fdt_add_subnode(blob, timings, "timing");
+
+ /* fill with useful values */
+ fdt_add_display_timings(blob, final, &mode);
+
+ return;
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ backlight_off();
+
+ setup_spi();
+
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+ leds_on();
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: "CONFIG_SYS_BOARD" "CONFIG_SYS_VARIANT"\n");
+ return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index c602a16..d5175f5 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -295,6 +295,7 @@ Active arm armv7 mx6 -
udoo udoo_qua
Active arm armv7 mx6 - wandboard
wandboard_dl
wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
Fabio Estevam
<fabio.este...@freescale.com>
Active arm armv7 mx6 - wandboard
wandboard_quad
wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048
Fabio Estevam
<fabio.este...@freescale.com>
Active arm armv7 mx6 - wandboard
wandboard_solo
wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512
Fabio Estevam
<fabio.este...@freescale.com>
+Active arm armv7 mx6 bachmann ot1200
ot1200_mr
ot1200:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,SYS_VARIANT="mr",MX6Q
Active arm armv7 mx6 boundary nitrogen6x
mx6qsabrelite
nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE
Eric Nelson
<eric.nel...@boundarydevices.com>
Active arm armv7 mx6 boundary nitrogen6x
nitrogen6dl
nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
Eric Nelson
<eric.nel...@boundarydevices.com>
Active arm armv7 mx6 boundary nitrogen6x
nitrogen6dl2g
nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048
Eric Nelson
<eric.nel...@boundarydevices.com>
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
new file mode 100644
index 0000000..1c1e5fc
--- /dev/null
+++ b/include/configs/ot1200.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Bachmann electronic GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* UART Configs */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE
+
+/* SF Configs */
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS 2
+#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(1, 3)<<8))
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+
+/* IO expander */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
+#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* OF Configs */
+#define CONFIG_I2C_EDID
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/* OCOTP Configs */
+#define CONFIG_CMD_IMXOTP
+#ifdef CONFIG_CMD_IMXOTP
+#define CONFIG_IMX_OTP
+#define IMX_OTP_BASE OCOTP_BASE_ADDR
+#define IMX_OTP_ADDR_MAX 0x7F
+#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
+#define IMX_OTPWRITE_ENABLED
+#endif
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE MII100
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 0x5
+#define CONFIG_PHYLIB
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 1
+
+#define CONFIG_PREBOOT ""
+
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "U-Boot > "
+#define CONFIG_SYS_CBSIZE 1024
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) /* TODO:
needed? */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE (8 * 1024) /* 8 kb */
+#define CONFIG_ENV_OFFSET (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE (8 * 1024)
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* FS Configs */
+#define CONFIG_CMD_EXT3
+#define CONFIG_CMD_EXT4
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FS_GENERIC
+
+/* needed for run-in etc. */
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_BOOTFILE
+
+/*
+ * Memory layout for where various images get loaded by boot scripts
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=0x14000000\0" \
+ "kernel_addr_r=0x10000000\0" \
+ "fdt_addr_r=0x11000000\0" \
+ "ramdisk_addr_r=0x12A00000\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+#ifdef CONFIG_CMD_MMC
+#define BOOTCMDS_MMC \
+ "mmc_boot=" \
+ "setenv devtype mmc; " \
+ "if mmc dev ${devnum}; then " \
+ "run scan_boot; " \
+ "fi\0" \
+ "bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0"
+#define BOOT_TARGETS_MMC "mmc0"
+#endif
+
+#define BOOTCMDS_COMMON \
+ "rootpart=2\0" \
+ \
+ "script_boot=" \
+ "if load ${devtype} ${devnum}:${rootpart} " \
+ "${scriptaddr} ${prefix}${script}; then " \
+ "echo ${script} found! Executing ...;" \
+ "source ${scriptaddr};" \
+ "fi;\0" \
+ \
+ "scan_boot=" \
+ "echo Scanning ${devtype} ${devnum}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "for script in ${boot_scripts}; do " \
+ "run script_boot; " \
+ "done; " \
+ "done;\0" \
+ \
+ "boot_targets=" \
+ BOOT_TARGETS_MMC " " \
+ "\0" \
+ \
+ "boot_prefixes=/boot/ \0" \
+ \
+ "boot_scripts=boot.scr\0" \
+ \
+ BOOTCMDS_MMC \
+
+#define CONFIG_BOOTCOMMAND \
+ "for target in ${boot_targets}; do run bootcmd_${target}; done"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "soc=imx6d\0" \
+ "board="CONFIG_SYS_BOARD"\0" \
+ "boardver="CONFIG_SYS_VARIANT"\0" \
+ MEM_LAYOUT_ENV_SETTINGS \
+ BOOTCMDS_COMMON
+
+#endif /* __CONFIG_H */
--
1.7.10.4
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