Hello Heiko, On 11/04/2013 10:53 AM, Heiko Schocher wrote: > Am 04.11.2013 09:53, schrieb Andreas Bießmann: >> On 11/04/2013 07:40 AM, Heiko Schocher wrote:
<snip> >>> + erstl = readl(&rstc->mr)& AT91_RSTC_MR_ERSTL_MASK; >>> + >>> + /* Need to reset PHY -> 500ms reset */ >>> + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | >>> + AT91_RSTC_MR_URSTEN,&rstc->mr); >>> + >>> + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST,&rstc->cr); >>> + >>> + /* Wait for end of reset */ >>> + at91_wait_for_reset(100); >> >> You say above, that this will be 500ms reset pulse ... but wait just >> 100ms. Is that Ok? >> Please also check the taurus board. > > We should rework this as Wolfgang suggested, or? Could you please give me a pointer? I can't remember what Wolfgang suggested here. Best regards Andreas Bießmann _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
