The macro allows easy setting in per-pin, as for example:
,----
| imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION);
`----
The IOMUX_CONFIG_SION allows for reading PAD value from PSR register.
The following quote from the datasheet:
,----
| ...
| 28.4.2.2 GPIO Write Mode
| The programming sequence for driving output signals should be as follows:
| 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need
| to read loopback pad value through PSR
| 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
| 3. Write value to data register (GPIO_DR).
| ...
`----
This fixes the gpio_get_value to properly work when a GPIO is set for
output and has no conflicts.
Thanks for Benoît Thébaudeau <benoit.thebaud...@advansee.com>, Fabio
Estevam <fabio.este...@freescale.com> and Eric Bénard
<e...@eukrea.com> for helping to properly trace this down.
Signed-off-by: Otavio Salvador <ota...@ossystems.com.br>
---
arch/arm/include/asm/imx-common/iomux-v3.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h
b/arch/arm/include/asm/imx-common/iomux-v3.h
index dc2b3ef..b7bdaa5 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -57,6 +57,7 @@ typedef u64 iomux_v3_cfg_t;
MUX_SEL_INPUT_OFS_SHIFT)
#define MUX_MODE_SHIFT 36
+#define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION <<
MUX_MODE_SHIFT)
#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
#define MUX_PAD_CTRL_SHIFT 41
#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
--
1.8.4.rc3
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