Stefano Babic wrote
> On 11/09/2013 15:30, Markus Niebel wrote:
>> From: Markus Niebel <
> Markus.Niebel@
> >
>>
>> according to the manual frequency of PLL2 PFD2 is 396.000.000
>> instead of 400.000.000
>>
>> Signed-off-by: Markus Niebel <
> Markus.Niebel@
> >
>> ---
>> arch/arm/include/asm/arch-mx6/crm_regs.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h
>> b/arch/arm/include/asm/arch-mx6/crm_regs.h
>> index 74aefe6..2813593 100644
>> --- a/arch/arm/include/asm/arch-mx6/crm_regs.h
>> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
>> @@ -892,7 +892,7 @@ struct mxc_ccm_reg {
>>
>> #define PLL2_PFD0_FREQ 352000000
>> #define PLL2_PFD1_FREQ 594000000
>> -#define PLL2_PFD2_FREQ 400000000
>> +#define PLL2_PFD2_FREQ 396000000
>> #define PLL2_PFD2_DIV_FREQ 200000000
>> #define PLL3_PFD0_FREQ 720000000
>> #define PLL3_PFD1_FREQ 540000000
>>
>
> Acked-by: Stefano Babic <
> sbabic@
> >
Hello Markus, Hello Stephano
I think it's better to compute this frequencies rather than hard coding
values. The default PFD frequencies are not the same for the Quad and for
the other Socs.
Furthermore, if you modify PLL2_PFD2_FREQ, you must also change
PLL2_PFD2_DIV_FREQ.
Please, see the patch I've submitted yesterday ([PATCH V2] mx6: compute PLL
PFD frequencies rather than using defines)
Best regards
--
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