From: Akshay Saraswat <aksha...@samsung.com>

Adds code in pinmux and gpio framework to support Exynos5420.

Signed-off-by: Rajeshwari S Shinde <rajeshwar...@samsung.com>
Signed-off-by: Akshay Saraswat <aksha...@samsung.com>
---
Changes in V2:
        - None
Changes in V3:
        - None
 arch/arm/cpu/armv7/exynos/pinmux.c      | 171 +++++++++++++++++++++++++++++++-
 arch/arm/include/asm/arch-exynos/gpio.h |  52 ++++++++++
 2 files changed, 220 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c 
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 1b05ebf..0382176 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -46,6 +46,41 @@ static void exynos5_uart_config(int peripheral)
        }
 }
 
+static void exynos5420_uart_config(int peripheral)
+{
+       struct exynos5420_gpio_part1 *gpio1 =
+               (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+       struct s5p_gpio_bank *bank;
+       int i, start, count;
+
+       switch (peripheral) {
+       case PERIPH_ID_UART0:
+               bank = &gpio1->a0;
+               start = 0;
+               count = 4;
+               break;
+       case PERIPH_ID_UART1:
+               bank = &gpio1->a0;
+               start = 4;
+               count = 4;
+               break;
+       case PERIPH_ID_UART2:
+               bank = &gpio1->a1;
+               start = 0;
+               count = 4;
+               break;
+       case PERIPH_ID_UART3:
+               bank = &gpio1->a1;
+               start = 4;
+               count = 2;
+               break;
+       }
+       for (i = start; i < start + count; i++) {
+               s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+               s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+       }
+}
+
 static int exynos5_mmc_config(int peripheral, int flags)
 {
        struct exynos5_gpio_part1 *gpio1 =
@@ -101,6 +136,62 @@ static int exynos5_mmc_config(int peripheral, int flags)
        return 0;
 }
 
+static int exynos5420_mmc_config(int peripheral, int flags)
+{
+       struct exynos5420_gpio_part3 *gpio3 =
+               (struct exynos5420_gpio_part3 *)samsung_get_base_gpio_part3();
+       struct s5p_gpio_bank *bank = NULL, *bank_ext = NULL;
+       int i, start = 0, gpio_func = 0;
+
+       switch (peripheral) {
+       case PERIPH_ID_SDMMC0:
+               bank = &gpio3->c0;
+               bank_ext = &gpio3->c3;
+               start = 0;
+               gpio_func = GPIO_FUNC(0x2);
+               break;
+       case PERIPH_ID_SDMMC1:
+               bank = &gpio3->c1;
+               bank_ext = &gpio3->d1;
+               start = 4;
+               gpio_func = GPIO_FUNC(0x2);
+               break;
+       case PERIPH_ID_SDMMC2:
+               bank = &gpio3->c2;
+               bank_ext = NULL;
+               gpio_func = GPIO_FUNC(0x2);
+               break;
+       }
+       if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+               debug("SDMMC device %d does not support 8bit mode",
+                               peripheral);
+               return -1;
+       }
+       if (flags & PINMUX_FLAG_8BIT_MODE) {
+               for (i = start; i <= (start + 3); i++) {
+                       s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
+                       s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
+                       s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+               }
+       }
+       for (i = 0; i < 3; i++) {
+               s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+               s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+               s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+       }
+
+       if (peripheral == PERIPH_ID_SDMMC0)
+               s5p_gpio_set_pull(bank, 2, GPIO_PULL_UP);
+
+       for (i = 3; i <= 6; i++) {
+               s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+               s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
+               s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+       }
+
+       return 0;
+}
+
 static void exynos5_sromc_config(int flags)
 {
        struct exynos5_gpio_part1 *gpio1 =
@@ -269,6 +360,49 @@ void exynos5_spi_config(int peripheral)
        }
 }
 
+void exynos5420_spi_config(int peripheral)
+{
+       int cfg = 0, pin = 0, i;
+       struct s5p_gpio_bank *bank = NULL;
+       struct exynos5420_gpio_part1 *gpio1 =
+               (struct exynos5420_gpio_part1 *)samsung_get_base_gpio_part1();
+       struct exynos5420_gpio_part4 *gpio4 =
+               (struct exynos5420_gpio_part4 *)samsung_get_base_gpio_part4();
+
+       switch (peripheral) {
+       case PERIPH_ID_SPI0:
+               bank = &gpio1->a2;
+               cfg = GPIO_FUNC(0x2);
+               pin = 0;
+               break;
+       case PERIPH_ID_SPI1:
+               bank = &gpio1->a2;
+               cfg = GPIO_FUNC(0x2);
+               pin = 4;
+               break;
+       case PERIPH_ID_SPI2:
+               bank = &gpio1->b1;
+               cfg = GPIO_FUNC(0x5);
+               pin = 1;
+               break;
+       case PERIPH_ID_SPI3:
+               bank = &gpio4->f1;
+               cfg = GPIO_FUNC(0x2);
+               pin = 0;
+               break;
+       case PERIPH_ID_SPI4:
+               for (i = 0; i < 2; i++) {
+                       s5p_gpio_cfg_pin(&gpio4->f0, i + 2, GPIO_FUNC(0x4));
+                       s5p_gpio_cfg_pin(&gpio4->e0, i + 4, GPIO_FUNC(0x4));
+               }
+               break;
+       }
+       if (peripheral != PERIPH_ID_SPI4) {
+               for (i = pin; i < pin + 4; i++)
+                       s5p_gpio_cfg_pin(bank, i, cfg);
+       }
+}
+
 static int exynos5_pinmux_config(int peripheral, int flags)
 {
        switch (peripheral) {
@@ -314,6 +448,35 @@ static int exynos5_pinmux_config(int peripheral, int flags)
        return 0;
 }
 
+static int exynos5420_pinmux_config(int peripheral, int flags)
+{
+       switch (peripheral) {
+       case PERIPH_ID_UART0:
+       case PERIPH_ID_UART1:
+       case PERIPH_ID_UART2:
+       case PERIPH_ID_UART3:
+               exynos5420_uart_config(peripheral);
+               break;
+       case PERIPH_ID_SDMMC0:
+       case PERIPH_ID_SDMMC1:
+       case PERIPH_ID_SDMMC2:
+       case PERIPH_ID_SDMMC3:
+               return exynos5420_mmc_config(peripheral, flags);
+       case PERIPH_ID_SPI0:
+       case PERIPH_ID_SPI1:
+       case PERIPH_ID_SPI2:
+       case PERIPH_ID_SPI3:
+       case PERIPH_ID_SPI4:
+               exynos5420_spi_config(peripheral);
+               break;
+       default:
+               debug("%s: invalid peripheral %d", __func__, peripheral);
+               return -1;
+       }
+
+       return 0;
+}
+
 static void exynos4_i2c_config(int peripheral, int flags)
 {
        struct exynos4_gpio_part1 *gpio1 =
@@ -463,11 +626,13 @@ static int exynos4_pinmux_config(int peripheral, int 
flags)
 
 int exynos_pinmux_config(int peripheral, int flags)
 {
-       if (cpu_is_exynos5())
+       if (cpu_is_exynos5()) {
+               if (proid_is_exynos5420())
+                       return exynos5420_pinmux_config(peripheral, flags);
                return exynos5_pinmux_config(peripheral, flags);
-       else if (cpu_is_exynos4())
+       } else if (cpu_is_exynos4()) {
                return exynos4_pinmux_config(peripheral, flags);
-       else {
+       } else {
                debug("pinmux functionality not supported\n");
                return -1;
        }
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h 
b/arch/arm/include/asm/arch-exynos/gpio.h
index a1a7439..f892933 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -127,6 +127,58 @@ struct exynos4x12_gpio_part4 {
        struct s5p_gpio_bank v4;
 };
 
+struct exynos5420_gpio_part1 {
+       struct s5p_gpio_bank a0;
+       struct s5p_gpio_bank a1;
+       struct s5p_gpio_bank a2;
+       struct s5p_gpio_bank b0;
+       struct s5p_gpio_bank b1;
+       struct s5p_gpio_bank b2;
+       struct s5p_gpio_bank b3;
+       struct s5p_gpio_bank b4;
+       struct s5p_gpio_bank h0;
+};
+
+struct exynos5420_gpio_part2 {
+       struct s5p_gpio_bank y7; /* 0x1340_0000 */
+       struct s5p_gpio_bank res[0x5f]; /*  */
+       struct s5p_gpio_bank x0; /* 0x1340_0C00 */
+       struct s5p_gpio_bank x1; /* 0x1340_0C20 */
+       struct s5p_gpio_bank x2; /* 0x1340_0C40 */
+       struct s5p_gpio_bank x3; /* 0x1340_0C60 */
+};
+
+struct exynos5420_gpio_part3 {
+       struct s5p_gpio_bank c0;
+       struct s5p_gpio_bank c1;
+       struct s5p_gpio_bank c2;
+       struct s5p_gpio_bank c3;
+       struct s5p_gpio_bank c4;
+       struct s5p_gpio_bank d1;
+       struct s5p_gpio_bank y0;
+       struct s5p_gpio_bank y1;
+       struct s5p_gpio_bank y2;
+       struct s5p_gpio_bank y3;
+       struct s5p_gpio_bank y4;
+       struct s5p_gpio_bank y5;
+       struct s5p_gpio_bank y6;
+};
+
+struct exynos5420_gpio_part4 {
+       struct s5p_gpio_bank e0; /* 0x1400_0000 */
+       struct s5p_gpio_bank e1; /* 0x1400_0020 */
+       struct s5p_gpio_bank f0; /* 0x1400_0040 */
+       struct s5p_gpio_bank f1; /* 0x1400_0060 */
+       struct s5p_gpio_bank g0; /* 0x1400_0080 */
+       struct s5p_gpio_bank g1; /* 0x1400_00A0 */
+       struct s5p_gpio_bank g2; /* 0x1400_00C0 */
+       struct s5p_gpio_bank j4; /* 0x1400_00E0 */
+};
+
+struct exynos5420_gpio_part5 {
+       struct s5p_gpio_bank z0; /* 0x0386_0000 */
+};
+
 struct exynos5_gpio_part1 {
        struct s5p_gpio_bank a0;
        struct s5p_gpio_bank a1;
-- 
1.7.12.4

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