-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 07/10/2013 09:23 AM, Nishanth Menon wrote: > On Wed, Jul 10, 2013 at 6:25 AM, Sourav Poddar > <sourav.pod...@ti.com> wrote: >> From: Matt Porter <mpor...@ti.com>
I think it's good form to update folks addresses, Matt is now matt.por...@linaro.org >> Add QSPI definitions and clock configuration support. [snip] >> diff --git a/arch/arm/include/asm/arch-omap5/spl.h >> b/arch/arm/include/asm/arch-omap5/spl.h index d4d353c..8905cb8 >> 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ >> b/arch/arm/include/asm/arch-omap5/spl.h @@ -31,6 +31,7 @@ >> #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 >> 6 #define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SPI 10 > > why not 8? This is the value ROM passes when we boot here. What I would like to know is, is this really "SPI" or QSPI_1 or QSPI_4 ? I suspect it's QSPI_1. And yes, we want to be precise here because while DRA7 doesn't have McSPI AM437x will, along with QSPI. - -- Tom -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQIcBAEBAgAGBQJR3WURAAoJENk4IS6UOR1W9aQP/jEBoyQKtU7n+B6aAMY5b5U4 FF54lAfRvJZfUaRVDCLmLMF+87Obx6ctQ95SogkKbsNmc5TxbDy7dBfd7G3++5ZG ivYQcEv9MKi/kGgJ0UZejc2J4e+QbQbymvnVqHG2mKJnMjRSdeuQG7UUGGIRQeA7 /VwR4cZuNqVrcejlglrBrwxr5PdA1f/cMCr1Dp4PhiHzxG+YYbiS4EVmnT+GNXmL RfZuy2TzjAir7brn4Y6sQ2fcHu2qXIzO6U/a16ZawfwB8089Zj4FMvP20IugsIyU drZhaJ3jY+leTCW1Wq5BZ1s2IJ7eaIqW4kbCSif9sPqxqM1lwJdqFJAdY8eGUWD/ c7cpJxkyLvleK0WFZDVraljIXoY7SMiTpnjYU5M+ASV43s+fFSl3f0VnZLuQtkkW +nFQeF1FdRDUd32jFDOzCuEeJbiPpy3mJLn60ND1r56VPQweroVBE3AetavzYDA0 K40Q3o/vXBLPyl2IELLOK5hpESWVlXasgMUOsNSfqpxGblh9ea5sXZ/Nvk8hjdmm ViVXk5lqNvmZzYzu0znRmLEg3ucuyYif0IOh/IOb97mAjR8KX0iCavw42RI5ympb E6d4is/Ap3x67BMBiEquRVWYmXv78Mr0o6LEhgayxM9rrT38uJyaGgIXlszia0xE QIqgV1U808hJVFMMnAK+ =EY5D -----END PGP SIGNATURE----- _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
