move s_init from every board code to a common place. Signed-off-by: Heiko Schocher <h...@denx.de> Cc: Tom Rini <tr...@ti.com> Cc: Matt Porter <mpor...@ti.com> Cc: Lars Poeschel <poesc...@lemonage.de> Cc: Tom Rini <tr...@ti.com> Cc: Enric Balletbo i Serra <eballe...@iseebcn.com>
--- This patch is based on the following patches: - [U-Boot,v2] arm, am33xx: move rtc32k_enable() to common place http://patchwork.ozlabs.org/patch/248908/ - [U-Boot] arm, am33xx: move uart soft reset code to common place http://patchwork.ozlabs.org/patch/248508/ - ./MAKEALL -s am33xx compiles without errors arch/arm/cpu/armv7/am33xx/board.c | 43 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-am33xx/sys_proto.h | 3 ++ board/isee/igep0033/board.c | 42 +++----------------------- board/phytec/pcm051/board.c | 45 ++++------------------------ board/ti/am335x/board.c | 43 ++++---------------------- 5 Dateien geändert, 60 Zeilen hinzugefügt(+), 116 Zeilen entfernt(-) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index b935a29..80b65fb 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -189,3 +189,46 @@ void uart_soft_reset(void) writel(regval, &uart_base->uartsyscfg); } #endif + +#ifndef CONFIG_TI81XX +static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + +void s_init(void) +{ + /* + * Save the boot parameters passed from romcode. + * We cannot delay the saving further than this, + * to prevent overwrites. + */ + save_omap_boot_params(); + + /* WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + +#ifdef CONFIG_SPL_BUILD + /* Setup the PLLs and the clocks for the peripherals */ + pll_init(); + + /* Enable RTC32K clock */ + rtc32k_enable(); + + /* early pinmux settings */ + board_enable_early_pinmux(); + + uart_soft_reset(); + + gd = &gdata; + + preloader_console_init(); + + sdram_init(); +#endif +} +#endif diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 307ac28..fffa549 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -45,4 +45,7 @@ void omap_nand_switch_ecc(uint32_t, uint32_t); void rtc32k_enable(void); void uart_soft_reset(void); +void board_enable_early_pinmux(void); +void sdram_init(void); + #endif diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 3be1084..2478a38 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; static const struct ddr_data ddr3_data = { @@ -69,55 +68,22 @@ static struct emif_regs ddr3_emif_reg_data = { .zq_config = K4B2G1646EBIH9_ZQ_CFG, .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY, }; -#endif /* * Early system init of muxing and clocks. */ -void s_init(void) +void board_enable_early_pinmux(void) { - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - -#ifdef CONFIG_SPL_BUILD - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); - - /* UART softreset */ - u32 regval; - enable_uart0_pin_mux(); +} - uart_soft_reset(); - gd = &gdata; - - preloader_console_init(); - +void sdram_init(void) +{ /* Configure board pin mux */ enable_board_pin_mux(); config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -#endif } /* diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 8940b44..df02b69 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -38,8 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - /* MII mode defines */ #define RMII_RGMII2_MODE_ENABLE 0x49 @@ -82,50 +80,17 @@ static struct emif_regs ddr3_emif_reg_data = { .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN, }; -#endif /* * early system init of muxing and clocks. */ -void s_init(void) +void board_enable_early_pinmux(void) { - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif - - /* - * WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - -#ifdef CONFIG_SPL_BUILD - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); - - /* UART softreset */ - u32 regval; - enable_uart0_pin_mux(); - uart_soft_reset(); - - gd = &gdata; - - preloader_console_init(); +} +void sdram_init(void) +{ /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); @@ -134,8 +99,8 @@ void s_init(void) config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 29528c4..2345013 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -37,8 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - /* GPIO that controls power to DDR on EVM-SK */ #define GPIO_DDR_VTT_EN 7 @@ -278,39 +276,11 @@ int spl_start_uboot(void) } #endif -#endif - /* * early system init of muxing and clocks. */ -void s_init(void) +void board_enable_early_pinmux(void) { - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - -#ifdef CONFIG_SPL_BUILD - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); - #ifdef CONFIG_SERIAL1 enable_uart0_pin_mux(); #endif /* CONFIG_SERIAL1 */ @@ -329,13 +299,10 @@ void s_init(void) #ifdef CONFIG_SERIAL6 enable_uart5_pin_mux(); #endif /* CONFIG_SERIAL6 */ +} - uart_soft_reset(); - - gd = &gdata; - - preloader_console_init(); - +void sdram_init(void) +{ /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); @@ -366,8 +333,8 @@ void s_init(void) else config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. -- 1.7.11.7 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
