Dear Fabio Estevam,
> From: Fabio Estevam <fabio.este...@freescale.com>
>
> HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as per
> FSL bootlets code.
>
> mx23 Reference Manual mark HW_DRAM_CTL27 and HW_DRAM_CTL28 as "reserved".
>
> HW_DRAM_CTL8 is setup as the last element.
>
> So skip the initialization of these DRAM_CTL registers.
>
> Signed-off-by: Fabio Estevam <fabio.este...@freescale.com>
> ---
> arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index cde883d..f500851 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> @@ -116,9 +116,12 @@ static void initialize_dram_values(void)
>
> mxs_adjust_memory_params(dram_vals);
>
> - for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
> - writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
> -
> + for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
> +#ifdef CONFIG_MX23
> + if (!(i == 8 || i == 27 || i == 28 || i == 35))
Stick a "continue" keyword here so it's contained instead of such a semi-
complete "if" clause please.
> +#endif
> + writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
> + }
> #ifdef CONFIG_MX23
> /*
> * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
Best regards,
Marek Vasut
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