From: Otavio Salvador <ota...@ossystems.com.br>
The MX23 has different handling of the SSP clock and GPMI NAND clock sources,
add necessary quirks into the clock code to properly handle these.
Signed-off-by: Marek Vasut <ma...@denx.de>
Signed-off-by: Otavio Salvador <ota...@ossystems.com.br>
Cc: Fabio Estevam <fabio.este...@freescale.com>
Cc: Stefano Babic <sba...@denx.de>
---
arch/arm/cpu/arm926ejs/mxs/clock.c | 44 +++++++++++++++++++++++++--------
arch/arm/include/asm/arch-mxs/clock.h | 8 ++++--
2 files changed, 40 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c
b/arch/arm/cpu/arm926ejs/mxs/clock.c
index b7cf98f..2df7ec6 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -1,5 +1,5 @@
/*
- * Freescale i.MX28 clock setup code
+ * Freescale i.MX23/i.MX28 clock setup code
*
* Copyright (C) 2011 Marek Vasut <marek.va...@gmail.com>
* on behalf of DENX Software Engineering GmbH
@@ -32,15 +32,24 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
-/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
+/*
+ * The PLL frequency is 480MHz and XTAL frequency is 24MHz
+ * iMX23: datasheet section 4.2
+ * iMX28: datasheet section 10.2
+ */
#define PLL_FREQ_KHZ 480000
#define PLL_FREQ_COEF 18
-/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
#define XTAL_FREQ_KHZ 24000
#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
+#if defined(CONFIG_MX23)
+#define MXC_SSPCLK_MAX MXC_SSPCLK0
+#elif defined(CONFIG_MX28)
+#define MXC_SSPCLK_MAX MXC_SSPCLK3
+#endif
+
static uint32_t mxs_get_pclk(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
@@ -120,10 +129,17 @@ static uint32_t mxs_get_gpmiclk(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
-
+#if defined(CONFIG_MX23)
+ uint8_t *reg =
+ &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
+#elif defined(CONFIG_MX28)
+ uint8_t *reg =
+ &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
+#endif
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
+
clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq);
clkctrl = readl(&clkctrl_regs->hw_clkctrl_gpmi);
@@ -134,7 +150,7 @@ static uint32_t mxs_get_gpmiclk(void)
}
/* REF Path */
- clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
+ clkfrac = readb(reg);
frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
@@ -203,7 +219,7 @@ void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq,
int xtal)
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clk, clkreg;
- if (ssp > MXC_SSPCLK3)
+ if (ssp > MXC_SSPCLK_MAX)
return;
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
@@ -248,7 +264,7 @@ static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
uint32_t clkreg;
uint32_t clk, tmp;
- if (ssp > MXC_SSPCLK3)
+ if (ssp > MXC_SSPCLK_MAX)
return 0;
tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
@@ -273,8 +289,14 @@ static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
*/
void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
{
+#if defined(CONFIG_MX23)
+ const unsigned int clkbus = 0;
+#elif defined(CONFIG_MX28)
+ const unsigned int clkbus = bus;
+#endif
+
struct mxs_ssp_regs *ssp_regs;
- const uint32_t sspclk = mxs_get_sspclk(bus);
+ const uint32_t sspclk = mxs_get_sspclk(clkbus);
uint32_t reg;
uint32_t divide, rate, tgtclk;
@@ -325,16 +347,18 @@ uint32_t mxc_get_clock(enum mxc_clock clk)
return mxs_get_ioclk(MXC_IOCLK0);
case MXC_IO1_CLK:
return mxs_get_ioclk(MXC_IOCLK1);
+ case MXC_XTAL_CLK:
+ return XTAL_FREQ_KHZ * 1000;
case MXC_SSP0_CLK:
return mxs_get_sspclk(MXC_SSPCLK0);
+#ifdef CONFIG_MX28
case MXC_SSP1_CLK:
return mxs_get_sspclk(MXC_SSPCLK1);
case MXC_SSP2_CLK:
return mxs_get_sspclk(MXC_SSPCLK2);
case MXC_SSP3_CLK:
return mxs_get_sspclk(MXC_SSPCLK3);
- case MXC_XTAL_CLK:
- return XTAL_FREQ_KHZ * 1000;
+#endif
}
return 0;
diff --git a/arch/arm/include/asm/arch-mxs/clock.h
b/arch/arm/include/asm/arch-mxs/clock.h
index d3927c7..3f7d3f0 100644
--- a/arch/arm/include/asm/arch-mxs/clock.h
+++ b/arch/arm/include/asm/arch-mxs/clock.h
@@ -1,5 +1,5 @@
/*
- * Freescale i.MX28 Clock
+ * Freescale i.MX23/i.MX28 Clock
*
* Copyright (C) 2011 Marek Vasut <marek.va...@gmail.com>
* on behalf of DENX Software Engineering GmbH
@@ -31,11 +31,13 @@ enum mxc_clock {
MXC_GPMI_CLK,
MXC_IO0_CLK,
MXC_IO1_CLK,
+ MXC_XTAL_CLK,
MXC_SSP0_CLK,
+#ifdef CONFIG_MX28
MXC_SSP1_CLK,
MXC_SSP2_CLK,
MXC_SSP3_CLK,
- MXC_XTAL_CLK,
+#endif
};
enum mxs_ioclock {
@@ -45,9 +47,11 @@ enum mxs_ioclock {
enum mxs_sspclock {
MXC_SSPCLK0 = 0,
+#ifdef CONFIG_MX28
MXC_SSPCLK1,
MXC_SSPCLK2,
MXC_SSPCLK3,
+#endif
};
uint32_t mxc_get_clock(enum mxc_clock clk);
--
1.7.10.4
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