From: Alexey Brodkin <abrod...@synopsys.com>
Current implementation works fine for bus width = 16 bits because we
never get into "if" branch.
If one sets width to 8 bits there will be 2 consequent data accesses
(read/write):
1. Correct data access for 8-bit bus
2. Unconditional (and in this case incorrect) data access as if data bus
is 16-bit wide
Signed-off-by: Alexey Brodkin <abrod...@synopsys.com>
---
drivers/block/systemace.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/block/systemace.c b/drivers/block/systemace.c
index 247cf06..88561a7 100644
--- a/drivers/block/systemace.c
+++ b/drivers/block/systemace.c
@@ -66,7 +66,8 @@ static void ace_writew(u16 val, unsigned off)
writeb(val >> 8, base + off + 1);
#endif
}
- out16(base + off, val);
+ else
+ out16(base + off, val);
}
static u16 ace_readw(unsigned off)
@@ -78,8 +79,8 @@ static u16 ace_readw(unsigned off)
return readb(base + off) | (readb(base + off + 1) << 8);
#endif
}
-
- return in16(base + off);
+ else
+ return in16(base + off);
}
static unsigned long systemace_read(int dev, unsigned long start,
--
1.7.10.4
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