Hi Tom,
I have included a config change 'Fix coreboot config to boot on
Chromebook' as I found after all this work that it did not actually
boot correctly without this. I hope that is ok. This should be the
final pull request for x86 until 'next' opens.
The following changes since commit 468ebf190a737dd1021ca15ff350ceee2001372e:
4xx: Fix PCI memory mapping on CPCI405 boards (2012-12-06 15:53:04 +0100)
are available in the git repository at:
git://git.denx.de/u-boot-x86.git master
Bill Richardson (2):
x86: gpio: Add GPIO driver for Intel ICH6 and later.
x86: gpio: Add additional GPIO banks to the ICH6 driver
Duncan Laurie (5):
x86: Ignore memory >4GB when parsing Coreboot tables
x86: Fix off-by-one error in do_elf_reloc_fixups()
x86: Fix MTRR clear to detect which MTRR to use
x86: Issue SMI to finalize Coreboot in final stage
video: Check for valid FB pointer before clearing
Gabe Black (13):
x86: Fill in the dram info using the e820 map on coreboot/x86
x86: Increase the size of the phys_size_t and phys_addr_t types
Introduce arch_phys_memset which works like memset but on physical memory
x86: Implement arch_phys_memset so that it can wipe memory above 4GB
x86: Initialise SPI if enabled
x86: Reorder x86's post relocation memory layout
x86: Make the upper bound on relocated symbols closed instead of open
x86: Make calculate_relocation_address an overridable function
x86: Override calculate_relocation_address to use the e820 map
x86: Add back cold- and warm-boot flags
x86: Add support for CONFIG_OF_CONTROL
x86: coreboot: Set CONFIG_ARCH_DEVICE_TREE correctly
x86: Turn on support for EFI's GPT in the coreboot config
Graeme Russ (1):
x86: Import MSR/MTRR code from Linux
Simon Glass (8):
x86: Enable ICH6 GPIO controller for coreboot
x86: Fix indirect jmp warning in zimage.c
x86: Enable CONFIG_CMD_ZBOOT for coreboot
x86: fdt: Create basic .dtsi file for coreboot
x86: Remove video_init() prototype from u-boot-x86.h
x86: Build vga video code only if CONFIG_VIDEO_VGA is defined
x86: coreboot: Enable video display
x86: Fix coreboot config to boot on Chromebook
Stefan Reinauer (7):
x86: Add basic cache operations
x86: Provide a function to clean up just before booting a zimage
x86: Clean up MTRR 7 right before jumping to the kernel
x86: Add CONFIG_DELAY_ENVIRONMENT to delay environment loading
x86: Emit port 80 post codes in show_boot_progress()
x86: Remove coreboot_ from file name
x86: drop unused code in coreboot.c
Vadim Bendebury (5):
x86: Add function to read time stamp counter
x86: Enable coreboot timestamp facility support in u-boot.
x86: Add a CBMEM timestamp generated right before the kernel startup.
x86: Provide tick counter and frequency reference for Intel core
architecture
x86: Provide a way to throttle port80 accesses
README | 15 +
arch/x86/cpu/coreboot/Makefile | 4 +-
arch/x86/cpu/coreboot/{coreboot_car.S => car.S} | 0
arch/x86/cpu/coreboot/config.mk | 23 +
arch/x86/cpu/coreboot/coreboot.c | 61 +++-
arch/x86/cpu/coreboot/sdram.c | 72 +++-
arch/x86/cpu/coreboot/timestamp.c | 61 +++
arch/x86/cpu/cpu.c | 38 ++-
arch/x86/cpu/interrupts.c | 99 ++---
arch/x86/cpu/start.S | 10 +-
arch/x86/cpu/start16.S | 3 +
arch/x86/dts/coreboot.dtsi | 16 +
arch/x86/dts/skeleton.dtsi | 13 +
arch/x86/include/asm/arch-coreboot/timestamp.h | 52 +++
arch/x86/include/asm/cache.h | 16 +
arch/x86/include/asm/control_regs.h | 105 +++++
arch/x86/include/asm/global_data.h | 6 +
arch/x86/include/asm/gpio.h | 27 ++
arch/x86/include/asm/init_helpers.h | 1 +
arch/x86/include/asm/io.h | 6 +-
arch/x86/include/asm/msr-index.h | 469 ++++++++++++++++++++
arch/x86/include/asm/msr.h | 238 ++++++++++
arch/x86/include/asm/mtrr.h | 206 +++++++++
arch/x86/include/asm/types.h | 4 +-
arch/x86/include/asm/u-boot-x86.h | 13 +-
arch/x86/lib/Makefile | 5 +-
arch/x86/lib/board.c | 10 +
arch/x86/lib/init_helpers.c | 48 ++-
arch/x86/lib/init_wrappers.c | 28 ++-
arch/x86/lib/physmem.c | 228 ++++++++++
arch/x86/lib/relocate.c | 4 +-
arch/x86/lib/timer.c | 17 +
arch/x86/lib/zimage.c | 23 +-
.../chromebook-x86/dts/{x86-alex.dts => alex.dts} | 18 +-
board/chromebook-x86/dts/link.dts | 24 +
boards.cfg | 2 +-
drivers/gpio/Makefile | 1 +
drivers/gpio/intel_ich6_gpio.c | 290 ++++++++++++
drivers/video/cfb_console.c | 2 +
include/configs/coreboot.h | 48 ++-
include/pci.h | 123 +++++
include/physmem.h | 21 +
lib/Makefile | 1 +
lib/physmem.c | 24 +
44 files changed, 2347 insertions(+), 128 deletions(-)
rename arch/x86/cpu/coreboot/{coreboot_car.S => car.S} (100%)
create mode 100644 arch/x86/cpu/coreboot/config.mk
create mode 100644 arch/x86/cpu/coreboot/timestamp.c
create mode 100644 arch/x86/dts/coreboot.dtsi
create mode 100644 arch/x86/dts/skeleton.dtsi
create mode 100644 arch/x86/include/asm/arch-coreboot/timestamp.h
create mode 100644 arch/x86/include/asm/control_regs.h
create mode 100644 arch/x86/include/asm/gpio.h
create mode 100644 arch/x86/include/asm/msr-index.h
create mode 100644 arch/x86/include/asm/msr.h
create mode 100644 arch/x86/include/asm/mtrr.h
create mode 100644 arch/x86/lib/physmem.c
rename board/chromebook-x86/dts/{x86-alex.dts => alex.dts} (53%)
create mode 100644 board/chromebook-x86/dts/link.dts
create mode 100644 drivers/gpio/intel_ich6_gpio.c
create mode 100644 include/physmem.h
create mode 100644 lib/physmem.c
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