---------- Forwarded message ----------
From: arun sharma <arun.co...@gmail.com>
Date: Fri, Feb 13, 2009 at 4:57 PM
Subject: registered SORDIMM MT9HTF6472RHY-667F1
To: u-boot@lists.denx.de
i am using mpc8360 emds board.
it is working fine with socdimm.
but with sordimm not working.
there is minor change i have done it for sordimm as follows for testing
only.
/* sdram_cfg[3] = RD_EN - registered DIMM enable */
// if (spd.mod_attr & 0x02) vivek
// {
printf("sdramcfg[3] registered DIMM\n");
sdram_cfg |= SDRAM_CFG_RD_EN;
// }
//#if defined(CONFIG_DDR_2T_TIMING) vivek
/*
* Enable 2T timing by setting sdram_cfg[16].
*/
// sdram_cfg |= SDRAM_CFG_2T_EN;
//#endif
i have enabled spd_debug and check the configuration.
CPU: e300c1, MPC8358_TBGA_EA, Rev: 2.1 at 396 MHz, CSB: 198 MHz
Board: Freescale MPC8360EMDS
I2C: ready
DRAM:
DIMM type: 9HTF6472RHY-667F1
SPD size: 128
EEPROM size: 256
Memory type: 8
Row addr: 14
Column addr: 10
# of rows: 96
Row density: 128
# of banks: 4
Data width: 72
Chip width: 8
Refresh rate: 82
CAS latencies: 38
Write latencies: 04
tRP: 60
tRCD: 60
cs0_bnds = 0x0000001f
cs0_config = 0x80010202
DDR:bar=0x00000000
DDR:ar=0x8000001c
DDR: caslat SPD bit is 5
DDR:Module maximum data rate is: 666 MHz
DDR:Effective data rate is: 200MHz
DDR:The MSB 1 of CAS Latency is: 5
DDR: effective data rate is 200 MHz
DDR: caslat SPD bit is 5, controller field is 0x9
DDR: timing_cfg_0 = 0x00260802
DDR:timing_cfg_1=0x25293211
DDR:timing_cfg_2=0x0fa028c4
DDR DIMM: data bus width is 64 bit with ECC
DDR:sdram_mode=0x04400252
DDR: sdram_mode2 = 0x00000000
DDR:sdram_interval=0x03050100
DDR: sdram_cfg2 = 0x00401000
DDR:sdram_clk_cntl=0x02000000
sdramcfg[3] registered DIMM
DDR:err_disable=0x0000000d
DDR:err_sbe=0x00ff0000
DDRC ECC mode: ON
DDR:sdram_cfg=0xf3000000
ddr init: CPU FP write method
READY!!
ddr init duration: 2090 ms
512 MB (DDR2, 64-bit, ECC on, 198 MHz)
Testing DRAM from 0x00000000 to 0x00200000
DRAM test phase 1:
write done
DRAM test phase 2:
DRAM test passed.
regards
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