This patch adds flush_/invalidate_dcache_range() to the MIPS architecture.
Those functions are needed for the upcoming dcache support for the USB
EHCI driver. I chose this API because those cache handling functions are
already present in the PPC architecture.
Signed-off-by: Stefan Roese <s...@denx.de>
---
cpu/mips/cpu.c | 28 ++++++++++++++++++++++++++++
include/common.h | 2 ++
2 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index b7180b0..d5a1604 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -65,6 +65,34 @@ void flush_cache(ulong start_addr, ulong size)
}
}
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+ while (1) {
+ cache_op(Hit_Invalidate_D, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
{
write_c0_entrylo0(low0);
diff --git a/include/common.h b/include/common.h
index 18687c6..3bf60a2 100644
--- a/include/common.h
+++ b/include/common.h
@@ -597,6 +597,8 @@ ulong video_setmem (ulong);
/* lib_$(ARCH)/cache.c */
void flush_cache (unsigned long, unsigned long);
+void flush_dcache_range(unsigned long start, unsigned long stop);
+void invalidate_dcache_range(unsigned long start, unsigned long stop);
/* lib_$(ARCH)/ticks.S */
--
1.6.1
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