Dave Liu wrote: > - It is possible to miss flush/invalidate the last > cache line, we fix it at here.
That comment was on the version you posted in the NAND patch; the lib_ppc version actually looks worse -- it tried to round down to avoid the issue, but it was missing a ~. Thus, it flushed everything from address 0 to the end. > + start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); > + end = (start_addr + size) & ~(CONFIG_SYS_CACHELINE_SIZE - 1); end = start_addr + size - 1; The rounding is unnecessary for end, and without the - 1, if start_addr + size is on a cacheline boundary, you'll flush one cache line too many (which might not be mapped, or might cause end to wrap around to zero if flushing at the end of the address space). -Scott _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
