Klemens Nanni <k...@openbsd.org> wrote: > On Sat, Oct 12, 2019 at 09:53:44AM -0600, Theo de Raadt wrote: > > I am suggesting you put the spaces after the cpu#. > Is this better? > > 4 CPUs: 0.0% user, 0.0% nice, 0.0% sys, 0.0% spin, 0.0% intr, 100% > idle > > CPU 0 : 0.0% user, 0.0% nice, 0.0% sys, 0.0% spin, 0.0% intr, 100% > idle > CPU 1 : 0.0% user, 0.0% nice, 0.0% sys, 0.0% spin, 0.0% intr, 100% > idle > CPU 2 : 0.0% user, 0.0% nice, 0.0% sys, 0.0% spin, 0.0% intr, 100% > idle > CPU 3 : 1.1% user, 0.0% nice, 0.0% sys, 0.0% spin, 0.0% intr, 98.9% > idle
Shall I send a corresponding diff to the kernel? cpu 0: Intel(R) Xeon(R) Silver 4112 CPU @ 2.60GHz, 2893.92 MHz, 06-55-04 cpu 0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,DTES64,MWAIT,DS-CPL,VMX,SMX,EST,TM2,SSSE3,SDBG,FMA3,CX16,xTPR,PDCM,PCID,DCA,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,DEADLINE,AES,XSAVE,AVX,F16C,RDRAND,NXE,PAGE1GB,RDTSCP,LONG,LAHF,ABM,3DNOWP,PERF,ITSC,FSGSBASE,TSC_ADJUST,BMI1,HLE,AVX2,SMEP,BMI2,ERMS,INVPCID,RTM,PQM,MPX,AVX512F,AVX512DQ,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,PT,AVX512CD,AVX512BW,AVX512VL,PKU,MD_CLEAR,TSXFA,IBRS,IBPB,STIBP,L1DF,SSBD,SENSOR,ARAT,XSAVEOPT,XSAVEC,XGETBV1,XSAVES,MELTDOWN cpu 0: 256KB 64b/line 8-way L2 cache tsc_timecounter_init: TSC skew=0 observed drift=0 cpu 0: smt 0, core 1, package 0 I'm saying I don't understand your choice of columns.
